Robobo
component_rtc.h
1 /* ----------------------------------------------------------------------------
2  * SAM Software Package License
3  * ----------------------------------------------------------------------------
4  * Copyright (c) 2012, Atmel Corporation
5  *
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following condition is met:
10  *
11  * - Redistributions of source code must retain the above copyright notice,
12  * this list of conditions and the disclaimer below.
13  *
14  * Atmel's name may not be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
20  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
23  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  * ----------------------------------------------------------------------------
28  */
29 
30 #ifndef _SAM3U_RTC_COMPONENT_
31 #define _SAM3U_RTC_COMPONENT_
32 
33 /* ============================================================================= */
35 /* ============================================================================= */
38 
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40 
41 typedef struct {
42  RwReg RTC_CR;
43  RwReg RTC_MR;
44  RwReg RTC_TIMR;
45  RwReg RTC_CALR;
46  RwReg RTC_TIMALR;
47  RwReg RTC_CALALR;
48  RoReg RTC_SR;
49  WoReg RTC_SCCR;
50  WoReg RTC_IER;
51  WoReg RTC_IDR;
52  RoReg RTC_IMR;
53  RoReg RTC_VER;
54  RoReg Reserved1[45];
55  RwReg RTC_WPMR;
56 } Rtc;
57 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
58 /* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
59 #define RTC_CR_UPDTIM (0x1u << 0)
60 #define RTC_CR_UPDCAL (0x1u << 1)
61 #define RTC_CR_TIMEVSEL_Pos 8
62 #define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos)
63 #define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8)
64 #define RTC_CR_TIMEVSEL_HOUR (0x1u << 8)
65 #define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8)
66 #define RTC_CR_TIMEVSEL_NOON (0x3u << 8)
67 #define RTC_CR_CALEVSEL_Pos 16
68 #define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos)
69 #define RTC_CR_CALEVSEL_WEEK (0x0u << 16)
70 #define RTC_CR_CALEVSEL_MONTH (0x1u << 16)
71 #define RTC_CR_CALEVSEL_YEAR (0x2u << 16)
72 /* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
73 #define RTC_MR_HRMOD (0x1u << 0)
74 /* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
75 #define RTC_TIMR_SEC_Pos 0
76 #define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos)
77 #define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
78 #define RTC_TIMR_MIN_Pos 8
79 #define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos)
80 #define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
81 #define RTC_TIMR_HOUR_Pos 16
82 #define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos)
83 #define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
84 #define RTC_TIMR_AMPM (0x1u << 22)
85 /* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
86 #define RTC_CALR_CENT_Pos 0
87 #define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos)
88 #define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
89 #define RTC_CALR_YEAR_Pos 8
90 #define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos)
91 #define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
92 #define RTC_CALR_MONTH_Pos 16
93 #define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos)
94 #define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
95 #define RTC_CALR_DAY_Pos 21
96 #define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos)
97 #define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
98 #define RTC_CALR_DATE_Pos 24
99 #define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos)
100 #define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
101 /* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
102 #define RTC_TIMALR_SEC_Pos 0
103 #define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos)
104 #define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
105 #define RTC_TIMALR_SECEN (0x1u << 7)
106 #define RTC_TIMALR_MIN_Pos 8
107 #define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos)
108 #define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
109 #define RTC_TIMALR_MINEN (0x1u << 15)
110 #define RTC_TIMALR_HOUR_Pos 16
111 #define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos)
112 #define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
113 #define RTC_TIMALR_AMPM (0x1u << 22)
114 #define RTC_TIMALR_HOUREN (0x1u << 23)
115 /* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
116 #define RTC_CALALR_MONTH_Pos 16
117 #define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos)
118 #define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
119 #define RTC_CALALR_MTHEN (0x1u << 23)
120 #define RTC_CALALR_DATE_Pos 24
121 #define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos)
122 #define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
123 #define RTC_CALALR_DATEEN (0x1u << 31)
124 /* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
125 #define RTC_SR_ACKUPD (0x1u << 0)
126 #define RTC_SR_ALARM (0x1u << 1)
127 #define RTC_SR_SEC (0x1u << 2)
128 #define RTC_SR_TIMEV (0x1u << 3)
129 #define RTC_SR_CALEV (0x1u << 4)
130 /* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
131 #define RTC_SCCR_ACKCLR (0x1u << 0)
132 #define RTC_SCCR_ALRCLR (0x1u << 1)
133 #define RTC_SCCR_SECCLR (0x1u << 2)
134 #define RTC_SCCR_TIMCLR (0x1u << 3)
135 #define RTC_SCCR_CALCLR (0x1u << 4)
136 /* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
137 #define RTC_IER_ACKEN (0x1u << 0)
138 #define RTC_IER_ALREN (0x1u << 1)
139 #define RTC_IER_SECEN (0x1u << 2)
140 #define RTC_IER_TIMEN (0x1u << 3)
141 #define RTC_IER_CALEN (0x1u << 4)
142 /* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
143 #define RTC_IDR_ACKDIS (0x1u << 0)
144 #define RTC_IDR_ALRDIS (0x1u << 1)
145 #define RTC_IDR_SECDIS (0x1u << 2)
146 #define RTC_IDR_TIMDIS (0x1u << 3)
147 #define RTC_IDR_CALDIS (0x1u << 4)
148 /* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
149 #define RTC_IMR_ACK (0x1u << 0)
150 #define RTC_IMR_ALR (0x1u << 1)
151 #define RTC_IMR_SEC (0x1u << 2)
152 #define RTC_IMR_TIM (0x1u << 3)
153 #define RTC_IMR_CAL (0x1u << 4)
154 /* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
155 #define RTC_VER_NVTIM (0x1u << 0)
156 #define RTC_VER_NVCAL (0x1u << 1)
157 #define RTC_VER_NVTIMALR (0x1u << 2)
158 #define RTC_VER_NVCALALR (0x1u << 3)
159 /* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protect Mode Register -------- */
160 #define RTC_WPMR_WPEN (0x1u << 0)
161 #define RTC_WPMR_WPKEY_Pos 8
162 #define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos)
163 #define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))
164 
168 #endif /* _SAM3U_RTC_COMPONENT_ */
RwReg
volatile uint32_t RwReg
Definition: sam3n00a.h:54
WoReg
volatile uint32_t WoReg
Definition: sam3n00a.h:53
RoReg
volatile const uint32_t RoReg
Definition: sam3n00a.h:49
Rtc
Rtc hardware registers.
Definition: component_rtc.h:41