Robobo
component_supc.h
1 /* ----------------------------------------------------------------------------
2  * SAM Software Package License
3  * ----------------------------------------------------------------------------
4  * Copyright (c) 2012, Atmel Corporation
5  *
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following condition is met:
10  *
11  * - Redistributions of source code must retain the above copyright notice,
12  * this list of conditions and the disclaimer below.
13  *
14  * Atmel's name may not be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
20  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
23  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  * ----------------------------------------------------------------------------
28  */
29 
30 #ifndef _SAM3U_SUPC_COMPONENT_
31 #define _SAM3U_SUPC_COMPONENT_
32 
33 /* ============================================================================= */
35 /* ============================================================================= */
38 
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40 
41 typedef struct {
42  WoReg SUPC_CR;
43  RwReg SUPC_SMMR;
44  RwReg SUPC_MR;
45  RwReg SUPC_WUMR;
46  RwReg SUPC_WUIR;
47  RoReg SUPC_SR;
48 } Supc;
49 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
50 /* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
51 #define SUPC_CR_VROFF (0x1u << 2)
52 #define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2)
53 #define SUPC_CR_VROFF_STOP_VREG (0x1u << 2)
54 #define SUPC_CR_XTALSEL (0x1u << 3)
55 #define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3)
56 #define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3)
57 #define SUPC_CR_KEY_Pos 24
58 #define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos)
59 #define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
60 /* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
61 #define SUPC_SMMR_SMTH_Pos 0
62 #define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos)
63 #define SUPC_SMMR_SMTH_1_9V (0x0u << 0)
64 #define SUPC_SMMR_SMTH_2_0V (0x1u << 0)
65 #define SUPC_SMMR_SMTH_2_1V (0x2u << 0)
66 #define SUPC_SMMR_SMTH_2_2V (0x3u << 0)
67 #define SUPC_SMMR_SMTH_2_3V (0x4u << 0)
68 #define SUPC_SMMR_SMTH_2_4V (0x5u << 0)
69 #define SUPC_SMMR_SMTH_2_5V (0x6u << 0)
70 #define SUPC_SMMR_SMTH_2_6V (0x7u << 0)
71 #define SUPC_SMMR_SMTH_2_7V (0x8u << 0)
72 #define SUPC_SMMR_SMTH_2_8V (0x9u << 0)
73 #define SUPC_SMMR_SMTH_2_9V (0xAu << 0)
74 #define SUPC_SMMR_SMTH_3_0V (0xBu << 0)
75 #define SUPC_SMMR_SMTH_3_1V (0xCu << 0)
76 #define SUPC_SMMR_SMTH_3_2V (0xDu << 0)
77 #define SUPC_SMMR_SMTH_3_3V (0xEu << 0)
78 #define SUPC_SMMR_SMTH_3_4V (0xFu << 0)
79 #define SUPC_SMMR_SMSMPL_Pos 8
80 #define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos)
81 #define SUPC_SMMR_SMSMPL_SMD (0x0u << 8)
82 #define SUPC_SMMR_SMSMPL_CSM (0x1u << 8)
83 #define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8)
84 #define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8)
85 #define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8)
86 #define SUPC_SMMR_SMRSTEN (0x1u << 12)
87 #define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12)
88 #define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12)
89 #define SUPC_SMMR_SMIEN (0x1u << 13)
90 #define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13)
91 #define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13)
92 /* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
93 #define SUPC_MR_BODRSTEN (0x1u << 12)
94 #define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12)
95 #define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12)
96 #define SUPC_MR_BODDIS (0x1u << 13)
97 #define SUPC_MR_BODDIS_ENABLE (0x0u << 13)
98 #define SUPC_MR_BODDIS_DISABLE (0x1u << 13)
99 #define SUPC_MR_VDDIORDYONREG (0x1u << 14)
100 #define SUPC_MR_OSCBYPASS (0x1u << 20)
101 #define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20)
102 #define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20)
103 #define SUPC_MR_KEY_Pos 24
104 #define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos)
105 #define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
106 /* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
107 #define SUPC_WUMR_FWUPEN (0x1u << 0)
108 #define SUPC_WUMR_FWUPEN_NOT_ENABLE (0x0u << 0)
109 #define SUPC_WUMR_FWUPEN_ENABLE (0x1u << 0)
110 #define SUPC_WUMR_SMEN (0x1u << 1)
111 #define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1)
112 #define SUPC_WUMR_SMEN_ENABLE (0x1u << 1)
113 #define SUPC_WUMR_RTTEN (0x1u << 2)
114 #define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2)
115 #define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2)
116 #define SUPC_WUMR_RTCEN (0x1u << 3)
117 #define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3)
118 #define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3)
119 #define SUPC_WUMR_FWUPDBC_Pos 8
120 #define SUPC_WUMR_FWUPDBC_Msk (0x7u << SUPC_WUMR_FWUPDBC_Pos)
121 #define SUPC_WUMR_FWUPDBC_IMMEDIATE (0x0u << 8)
122 #define SUPC_WUMR_FWUPDBC_3_SCLK (0x1u << 8)
123 #define SUPC_WUMR_FWUPDBC_32_SCLK (0x2u << 8)
124 #define SUPC_WUMR_FWUPDBC_512_SCLK (0x3u << 8)
125 #define SUPC_WUMR_FWUPDBC_4096_SCLK (0x4u << 8)
126 #define SUPC_WUMR_FWUPDBC_32768_SCLK (0x5u << 8)
127 #define SUPC_WUMR_WKUPDBC_Pos 12
128 #define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos)
129 #define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12)
130 #define SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12)
131 #define SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12)
132 #define SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12)
133 #define SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12)
134 #define SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12)
135 /* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
136 #define SUPC_WUIR_WKUPEN0 (0x1u << 0)
137 #define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0u << 0)
138 #define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0)
139 #define SUPC_WUIR_WKUPEN1 (0x1u << 1)
140 #define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0u << 1)
141 #define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1)
142 #define SUPC_WUIR_WKUPEN2 (0x1u << 2)
143 #define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0u << 2)
144 #define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2)
145 #define SUPC_WUIR_WKUPEN3 (0x1u << 3)
146 #define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0u << 3)
147 #define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3)
148 #define SUPC_WUIR_WKUPEN4 (0x1u << 4)
149 #define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0u << 4)
150 #define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4)
151 #define SUPC_WUIR_WKUPEN5 (0x1u << 5)
152 #define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0u << 5)
153 #define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5)
154 #define SUPC_WUIR_WKUPEN6 (0x1u << 6)
155 #define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0u << 6)
156 #define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6)
157 #define SUPC_WUIR_WKUPEN7 (0x1u << 7)
158 #define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0u << 7)
159 #define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7)
160 #define SUPC_WUIR_WKUPEN8 (0x1u << 8)
161 #define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0u << 8)
162 #define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8)
163 #define SUPC_WUIR_WKUPEN9 (0x1u << 9)
164 #define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0u << 9)
165 #define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9)
166 #define SUPC_WUIR_WKUPEN10 (0x1u << 10)
167 #define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0u << 10)
168 #define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10)
169 #define SUPC_WUIR_WKUPEN11 (0x1u << 11)
170 #define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0u << 11)
171 #define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11)
172 #define SUPC_WUIR_WKUPEN12 (0x1u << 12)
173 #define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0u << 12)
174 #define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12)
175 #define SUPC_WUIR_WKUPEN13 (0x1u << 13)
176 #define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0u << 13)
177 #define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13)
178 #define SUPC_WUIR_WKUPEN14 (0x1u << 14)
179 #define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0u << 14)
180 #define SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14)
181 #define SUPC_WUIR_WKUPEN15 (0x1u << 15)
182 #define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0u << 15)
183 #define SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15)
184 #define SUPC_WUIR_WKUPT0 (0x1u << 16)
185 #define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16)
186 #define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16)
187 #define SUPC_WUIR_WKUPT1 (0x1u << 17)
188 #define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17)
189 #define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17)
190 #define SUPC_WUIR_WKUPT2 (0x1u << 18)
191 #define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18)
192 #define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18)
193 #define SUPC_WUIR_WKUPT3 (0x1u << 19)
194 #define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19)
195 #define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19)
196 #define SUPC_WUIR_WKUPT4 (0x1u << 20)
197 #define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20)
198 #define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20)
199 #define SUPC_WUIR_WKUPT5 (0x1u << 21)
200 #define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21)
201 #define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21)
202 #define SUPC_WUIR_WKUPT6 (0x1u << 22)
203 #define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22)
204 #define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22)
205 #define SUPC_WUIR_WKUPT7 (0x1u << 23)
206 #define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23)
207 #define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23)
208 #define SUPC_WUIR_WKUPT8 (0x1u << 24)
209 #define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24)
210 #define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24)
211 #define SUPC_WUIR_WKUPT9 (0x1u << 25)
212 #define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25)
213 #define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25)
214 #define SUPC_WUIR_WKUPT10 (0x1u << 26)
215 #define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26)
216 #define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26)
217 #define SUPC_WUIR_WKUPT11 (0x1u << 27)
218 #define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27)
219 #define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27)
220 #define SUPC_WUIR_WKUPT12 (0x1u << 28)
221 #define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28)
222 #define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28)
223 #define SUPC_WUIR_WKUPT13 (0x1u << 29)
224 #define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29)
225 #define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29)
226 #define SUPC_WUIR_WKUPT14 (0x1u << 30)
227 #define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30)
228 #define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30)
229 #define SUPC_WUIR_WKUPT15 (0x1u << 31)
230 #define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31)
231 #define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31)
232 /* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
233 #define SUPC_SR_FWUPS (0x1u << 0)
234 #define SUPC_SR_FWUPS_NO (0x0u << 0)
235 #define SUPC_SR_FWUPS_PRESENT (0x1u << 0)
236 #define SUPC_SR_WKUPS (0x1u << 1)
237 #define SUPC_SR_WKUPS_NO (0x0u << 1)
238 #define SUPC_SR_WKUPS_PRESENT (0x1u << 1)
239 #define SUPC_SR_SMWS (0x1u << 2)
240 #define SUPC_SR_SMWS_NO (0x0u << 2)
241 #define SUPC_SR_SMWS_PRESENT (0x1u << 2)
242 #define SUPC_SR_BODRSTS (0x1u << 3)
243 #define SUPC_SR_BODRSTS_NO (0x0u << 3)
244 #define SUPC_SR_BODRSTS_PRESENT (0x1u << 3)
245 #define SUPC_SR_SMRSTS (0x1u << 4)
246 #define SUPC_SR_SMRSTS_NO (0x0u << 4)
247 #define SUPC_SR_SMRSTS_PRESENT (0x1u << 4)
248 #define SUPC_SR_SMS (0x1u << 5)
249 #define SUPC_SR_SMS_NO (0x0u << 5)
250 #define SUPC_SR_SMS_PRESENT (0x1u << 5)
251 #define SUPC_SR_SMOS (0x1u << 6)
252 #define SUPC_SR_SMOS_HIGH (0x0u << 6)
253 #define SUPC_SR_SMOS_LOW (0x1u << 6)
254 #define SUPC_SR_OSCSEL (0x1u << 7)
255 #define SUPC_SR_OSCSEL_RC (0x0u << 7)
256 #define SUPC_SR_OSCSEL_CRYST (0x1u << 7)
257 #define SUPC_SR_FWUPIS (0x1u << 12)
258 #define SUPC_SR_FWUPIS_LOW (0x0u << 12)
259 #define SUPC_SR_FWUPIS_HIGH (0x1u << 12)
260 #define SUPC_SR_WKUPIS0 (0x1u << 16)
261 #define SUPC_SR_WKUPIS0_DIS (0x0u << 16)
262 #define SUPC_SR_WKUPIS0_EN (0x1u << 16)
263 #define SUPC_SR_WKUPIS1 (0x1u << 17)
264 #define SUPC_SR_WKUPIS1_DIS (0x0u << 17)
265 #define SUPC_SR_WKUPIS1_EN (0x1u << 17)
266 #define SUPC_SR_WKUPIS2 (0x1u << 18)
267 #define SUPC_SR_WKUPIS2_DIS (0x0u << 18)
268 #define SUPC_SR_WKUPIS2_EN (0x1u << 18)
269 #define SUPC_SR_WKUPIS3 (0x1u << 19)
270 #define SUPC_SR_WKUPIS3_DIS (0x0u << 19)
271 #define SUPC_SR_WKUPIS3_EN (0x1u << 19)
272 #define SUPC_SR_WKUPIS4 (0x1u << 20)
273 #define SUPC_SR_WKUPIS4_DIS (0x0u << 20)
274 #define SUPC_SR_WKUPIS4_EN (0x1u << 20)
275 #define SUPC_SR_WKUPIS5 (0x1u << 21)
276 #define SUPC_SR_WKUPIS5_DIS (0x0u << 21)
277 #define SUPC_SR_WKUPIS5_EN (0x1u << 21)
278 #define SUPC_SR_WKUPIS6 (0x1u << 22)
279 #define SUPC_SR_WKUPIS6_DIS (0x0u << 22)
280 #define SUPC_SR_WKUPIS6_EN (0x1u << 22)
281 #define SUPC_SR_WKUPIS7 (0x1u << 23)
282 #define SUPC_SR_WKUPIS7_DIS (0x0u << 23)
283 #define SUPC_SR_WKUPIS7_EN (0x1u << 23)
284 #define SUPC_SR_WKUPIS8 (0x1u << 24)
285 #define SUPC_SR_WKUPIS8_DIS (0x0u << 24)
286 #define SUPC_SR_WKUPIS8_EN (0x1u << 24)
287 #define SUPC_SR_WKUPIS9 (0x1u << 25)
288 #define SUPC_SR_WKUPIS9_DIS (0x0u << 25)
289 #define SUPC_SR_WKUPIS9_EN (0x1u << 25)
290 #define SUPC_SR_WKUPIS10 (0x1u << 26)
291 #define SUPC_SR_WKUPIS10_DIS (0x0u << 26)
292 #define SUPC_SR_WKUPIS10_EN (0x1u << 26)
293 #define SUPC_SR_WKUPIS11 (0x1u << 27)
294 #define SUPC_SR_WKUPIS11_DIS (0x0u << 27)
295 #define SUPC_SR_WKUPIS11_EN (0x1u << 27)
296 #define SUPC_SR_WKUPIS12 (0x1u << 28)
297 #define SUPC_SR_WKUPIS12_DIS (0x0u << 28)
298 #define SUPC_SR_WKUPIS12_EN (0x1u << 28)
299 #define SUPC_SR_WKUPIS13 (0x1u << 29)
300 #define SUPC_SR_WKUPIS13_DIS (0x0u << 29)
301 #define SUPC_SR_WKUPIS13_EN (0x1u << 29)
302 #define SUPC_SR_WKUPIS14 (0x1u << 30)
303 #define SUPC_SR_WKUPIS14_DIS (0x0u << 30)
304 #define SUPC_SR_WKUPIS14_EN (0x1u << 30)
305 #define SUPC_SR_WKUPIS15 (0x1u << 31)
306 #define SUPC_SR_WKUPIS15_DIS (0x0u << 31)
307 #define SUPC_SR_WKUPIS15_EN (0x1u << 31)
310 
311 
312 #endif /* _SAM3U_SUPC_COMPONENT_ */
volatile uint32_t RwReg
Definition: sam3n00a.h:54
volatile uint32_t WoReg
Definition: sam3n00a.h:53
Supc hardware registers.
Definition: component_supc.h:41
volatile const uint32_t RoReg
Definition: sam3n00a.h:49