component_usart.h

/* ----------------------------------------------------------------------------
 *         SAM Software Package License
 * ----------------------------------------------------------------------------
 * Copyright (c) 2012, Atmel Corporation
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following condition is met:
 *
 * - Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the disclaimer below.
 *
 * Atmel's name may not be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * ----------------------------------------------------------------------------
 */

#ifndef _SAM4S_USART_COMPONENT_
#define _SAM4S_USART_COMPONENT_

/* ============================================================================= */
/* ============================================================================= */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {
  WoReg US_CR;         
  RwReg US_MR;         
  WoReg US_IER;        
  WoReg US_IDR;        
  RoReg US_IMR;        
  RoReg US_CSR;        
  RoReg US_RHR;        
  WoReg US_THR;        
  RwReg US_BRGR;       
  RwReg US_RTOR;       
  RwReg US_TTGR;       
  RoReg Reserved1[5];
  RwReg US_FIDI;       
  RoReg US_NER;        
  RoReg Reserved2[1];
  RwReg US_IF;         
  RwReg US_MAN;        
  RoReg Reserved3[36];
  RwReg US_WPMR;       
  RoReg US_WPSR;       
  RoReg Reserved4[4];
  RoReg US_VERSION;    
  RwReg US_RPR;        
  RwReg US_RCR;        
  RwReg US_TPR;        
  RwReg US_TCR;        
  RwReg US_RNPR;       
  RwReg US_RNCR;       
  RwReg US_TNPR;       
  RwReg US_TNCR;       
  WoReg US_PTCR;       
  RoReg US_PTSR;       
} Usart;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
#define US_CR_RSTRX (0x1u << 2) 
#define US_CR_RSTTX (0x1u << 3) 
#define US_CR_RXEN (0x1u << 4) 
#define US_CR_RXDIS (0x1u << 5) 
#define US_CR_TXEN (0x1u << 6) 
#define US_CR_TXDIS (0x1u << 7) 
#define US_CR_RSTSTA (0x1u << 8) 
#define US_CR_STTBRK (0x1u << 9) 
#define US_CR_STPBRK (0x1u << 10) 
#define US_CR_STTTO (0x1u << 11) 
#define US_CR_SENDA (0x1u << 12) 
#define US_CR_RSTIT (0x1u << 13) 
#define US_CR_RSTNACK (0x1u << 14) 
#define US_CR_RETTO (0x1u << 15) 
#define US_CR_DTREN (0x1u << 16) 
#define US_CR_DTRDIS (0x1u << 17) 
#define US_CR_RTSEN (0x1u << 18) 
#define US_CR_FCS (0x1u << 18) 
#define US_CR_RTSDIS (0x1u << 19) 
#define US_CR_RCS (0x1u << 19) 
/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
#define US_MR_USART_MODE_Pos 0
#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) 
#define   US_MR_USART_MODE_NORMAL (0x0u << 0) 
#define   US_MR_USART_MODE_RS485 (0x1u << 0) 
#define   US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) 
#define   US_MR_USART_MODE_MODEM (0x3u << 0) 
#define   US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) 
#define   US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) 
#define   US_MR_USART_MODE_IRDA (0x8u << 0) 
#define   US_MR_USART_MODE_SPI_MASTER (0xEu << 0) 
#define   US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) 
#define US_MR_USCLKS_Pos 4
#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) 
#define   US_MR_USCLKS_MCK (0x0u << 4) 
#define   US_MR_USCLKS_DIV (0x1u << 4) 
#define   US_MR_USCLKS_SCK (0x3u << 4) 
#define US_MR_CHRL_Pos 6
#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) 
#define   US_MR_CHRL_5_BIT (0x0u << 6) 
#define   US_MR_CHRL_6_BIT (0x1u << 6) 
#define   US_MR_CHRL_7_BIT (0x2u << 6) 
#define   US_MR_CHRL_8_BIT (0x3u << 6) 
#define US_MR_SYNC (0x1u << 8) 
#define US_MR_CPHA (0x1u << 8) 
#define US_MR_PAR_Pos 9
#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) 
#define   US_MR_PAR_EVEN (0x0u << 9) 
#define   US_MR_PAR_ODD (0x1u << 9) 
#define   US_MR_PAR_SPACE (0x2u << 9) 
#define   US_MR_PAR_MARK (0x3u << 9) 
#define   US_MR_PAR_NO (0x4u << 9) 
#define   US_MR_PAR_MULTIDROP (0x6u << 9) 
#define US_MR_NBSTOP_Pos 12
#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) 
#define   US_MR_NBSTOP_1_BIT (0x0u << 12) 
#define   US_MR_NBSTOP_1_5_BIT (0x1u << 12) 
#define   US_MR_NBSTOP_2_BIT (0x2u << 12) 
#define US_MR_CHMODE_Pos 14
#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) 
#define   US_MR_CHMODE_NORMAL (0x0u << 14) 
#define   US_MR_CHMODE_AUTOMATIC (0x1u << 14) 
#define   US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) 
#define   US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) 
#define US_MR_MSBF (0x1u << 16) 
#define US_MR_CPOL (0x1u << 16) 
#define US_MR_MODE9 (0x1u << 17) 
#define US_MR_CLKO (0x1u << 18) 
#define US_MR_OVER (0x1u << 19) 
#define US_MR_INACK (0x1u << 20) 
#define US_MR_DSNACK (0x1u << 21) 
#define US_MR_VAR_SYNC (0x1u << 22) 
#define US_MR_INVDATA (0x1u << 23) 
#define US_MR_MAX_ITERATION_Pos 24
#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) 
#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
#define US_MR_FILTER (0x1u << 28) 
#define US_MR_MAN (0x1u << 29) 
#define US_MR_MODSYNC (0x1u << 30) 
#define US_MR_ONEBIT (0x1u << 31) 
/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
#define US_IER_RXRDY (0x1u << 0) 
#define US_IER_TXRDY (0x1u << 1) 
#define US_IER_RXBRK (0x1u << 2) 
#define US_IER_ENDRX (0x1u << 3) 
#define US_IER_ENDTX (0x1u << 4) 
#define US_IER_OVRE (0x1u << 5) 
#define US_IER_FRAME (0x1u << 6) 
#define US_IER_PARE (0x1u << 7) 
#define US_IER_TIMEOUT (0x1u << 8) 
#define US_IER_TXEMPTY (0x1u << 9) 
#define US_IER_ITER (0x1u << 10) 
#define US_IER_UNRE (0x1u << 10) 
#define US_IER_TXBUFE (0x1u << 11) 
#define US_IER_RXBUFF (0x1u << 12) 
#define US_IER_NACK (0x1u << 13) 
#define US_IER_RIIC (0x1u << 16) 
#define US_IER_DSRIC (0x1u << 17) 
#define US_IER_DCDIC (0x1u << 18) 
#define US_IER_CTSIC (0x1u << 19) 
#define US_IER_MANE (0x1u << 24) 
/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
#define US_IDR_RXRDY (0x1u << 0) 
#define US_IDR_TXRDY (0x1u << 1) 
#define US_IDR_RXBRK (0x1u << 2) 
#define US_IDR_ENDRX (0x1u << 3) 
#define US_IDR_ENDTX (0x1u << 4) 
#define US_IDR_OVRE (0x1u << 5) 
#define US_IDR_FRAME (0x1u << 6) 
#define US_IDR_PARE (0x1u << 7) 
#define US_IDR_TIMEOUT (0x1u << 8) 
#define US_IDR_TXEMPTY (0x1u << 9) 
#define US_IDR_ITER (0x1u << 10) 
#define US_IDR_UNRE (0x1u << 10) 
#define US_IDR_TXBUFE (0x1u << 11) 
#define US_IDR_RXBUFF (0x1u << 12) 
#define US_IDR_NACK (0x1u << 13) 
#define US_IDR_RIIC (0x1u << 16) 
#define US_IDR_DSRIC (0x1u << 17) 
#define US_IDR_DCDIC (0x1u << 18) 
#define US_IDR_CTSIC (0x1u << 19) 
#define US_IDR_MANE (0x1u << 24) 
/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
#define US_IMR_RXRDY (0x1u << 0) 
#define US_IMR_TXRDY (0x1u << 1) 
#define US_IMR_RXBRK (0x1u << 2) 
#define US_IMR_ENDRX (0x1u << 3) 
#define US_IMR_ENDTX (0x1u << 4) 
#define US_IMR_OVRE (0x1u << 5) 
#define US_IMR_FRAME (0x1u << 6) 
#define US_IMR_PARE (0x1u << 7) 
#define US_IMR_TIMEOUT (0x1u << 8) 
#define US_IMR_TXEMPTY (0x1u << 9) 
#define US_IMR_ITER (0x1u << 10) 
#define US_IMR_UNRE (0x1u << 10) 
#define US_IMR_TXBUFE (0x1u << 11) 
#define US_IMR_RXBUFF (0x1u << 12) 
#define US_IMR_NACK (0x1u << 13) 
#define US_IMR_RIIC (0x1u << 16) 
#define US_IMR_DSRIC (0x1u << 17) 
#define US_IMR_DCDIC (0x1u << 18) 
#define US_IMR_CTSIC (0x1u << 19) 
#define US_IMR_MANE (0x1u << 24) 
/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
#define US_CSR_RXRDY (0x1u << 0) 
#define US_CSR_TXRDY (0x1u << 1) 
#define US_CSR_RXBRK (0x1u << 2) 
#define US_CSR_ENDRX (0x1u << 3) 
#define US_CSR_ENDTX (0x1u << 4) 
#define US_CSR_OVRE (0x1u << 5) 
#define US_CSR_FRAME (0x1u << 6) 
#define US_CSR_PARE (0x1u << 7) 
#define US_CSR_TIMEOUT (0x1u << 8) 
#define US_CSR_TXEMPTY (0x1u << 9) 
#define US_CSR_ITER (0x1u << 10) 
#define US_CSR_UNRE (0x1u << 10) 
#define US_CSR_TXBUFE (0x1u << 11) 
#define US_CSR_RXBUFF (0x1u << 12) 
#define US_CSR_NACK (0x1u << 13) 
#define US_CSR_RIIC (0x1u << 16) 
#define US_CSR_DSRIC (0x1u << 17) 
#define US_CSR_DCDIC (0x1u << 18) 
#define US_CSR_CTSIC (0x1u << 19) 
#define US_CSR_RI (0x1u << 20) 
#define US_CSR_DSR (0x1u << 21) 
#define US_CSR_DCD (0x1u << 22) 
#define US_CSR_CTS (0x1u << 23) 
#define US_CSR_MANERR (0x1u << 24) 
/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
#define US_RHR_RXCHR_Pos 0
#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) 
#define US_RHR_RXSYNH (0x1u << 15) 
/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
#define US_THR_TXCHR_Pos 0
#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) 
#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
#define US_THR_TXSYNH (0x1u << 15) 
/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
#define US_BRGR_CD_Pos 0
#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) 
#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
#define US_BRGR_FP_Pos 16
#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) 
#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
#define US_RTOR_TO_Pos 0
#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) 
#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
#define US_TTGR_TG_Pos 0
#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) 
#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
#define US_FIDI_FI_DI_RATIO_Pos 0
#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) 
#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
#define US_NER_NB_ERRORS_Pos 0
#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) 
/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
#define US_IF_IRDA_FILTER_Pos 0
#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) 
#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */
#define US_MAN_TX_PL_Pos 0
#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) 
#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
#define US_MAN_TX_PP_Pos 8
#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) 
#define   US_MAN_TX_PP_ALL_ONE (0x0u << 8) 
#define   US_MAN_TX_PP_ALL_ZERO (0x1u << 8) 
#define   US_MAN_TX_PP_ZERO_ONE (0x2u << 8) 
#define   US_MAN_TX_PP_ONE_ZERO (0x3u << 8) 
#define US_MAN_TX_MPOL (0x1u << 12) 
#define US_MAN_RX_PL_Pos 16
#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) 
#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
#define US_MAN_RX_PP_Pos 24
#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) 
#define   US_MAN_RX_PP_ALL_ONE (0x0u << 24) 
#define   US_MAN_RX_PP_ALL_ZERO (0x1u << 24) 
#define   US_MAN_RX_PP_ZERO_ONE (0x2u << 24) 
#define   US_MAN_RX_PP_ONE_ZERO (0x3u << 24) 
#define US_MAN_RX_MPOL (0x1u << 28) 
#define US_MAN_STUCKTO1 (0x1u << 29) 
#define US_MAN_DRIFT (0x1u << 30) 
/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
#define US_WPMR_WPEN (0x1u << 0) 
#define US_WPMR_WPKEY_Pos 8
#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) 
#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
#define US_WPSR_WPVS (0x1u << 0) 
#define US_WPSR_WPVSRC_Pos 8
#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) 
/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */
#define US_VERSION_VERSION_Pos 0
#define US_VERSION_VERSION_Msk (0xfffu << US_VERSION_VERSION_Pos) 
#define US_VERSION_MFN_Pos 16
#define US_VERSION_MFN_Msk (0x7u << US_VERSION_MFN_Pos) 
/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
#define US_RPR_RXPTR_Pos 0
#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) 
#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))
/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
#define US_RCR_RXCTR_Pos 0
#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) 
#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))
/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
#define US_TPR_TXPTR_Pos 0
#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) 
#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))
/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
#define US_TCR_TXCTR_Pos 0
#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) 
#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))
/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
#define US_RNPR_RXNPTR_Pos 0
#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) 
#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))
/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
#define US_RNCR_RXNCTR_Pos 0
#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) 
#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))
/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
#define US_TNPR_TXNPTR_Pos 0
#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) 
#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))
/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
#define US_TNCR_TXNCTR_Pos 0
#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) 
#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))
/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
#define US_PTCR_RXTEN (0x1u << 0) 
#define US_PTCR_RXTDIS (0x1u << 1) 
#define US_PTCR_TXTEN (0x1u << 8) 
#define US_PTCR_TXTDIS (0x1u << 9) 
/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
#define US_PTSR_RXTEN (0x1u << 0) 
#define US_PTSR_TXTEN (0x1u << 8) 


#endif /* _SAM4S_USART_COMPONENT_ */