30 #ifndef _SAM3S8_PMC_INSTANCE_ 31 #define _SAM3S8_PMC_INSTANCE_ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_PMC_SCER (0x400E0400U) 36 #define REG_PMC_SCDR (0x400E0404U) 37 #define REG_PMC_SCSR (0x400E0408U) 38 #define REG_PMC_PCER0 (0x400E0410U) 39 #define REG_PMC_PCDR0 (0x400E0414U) 40 #define REG_PMC_PCSR0 (0x400E0418U) 41 #define REG_CKGR_MOR (0x400E0420U) 42 #define REG_CKGR_MCFR (0x400E0424U) 43 #define REG_CKGR_PLLAR (0x400E0428U) 44 #define REG_CKGR_PLLBR (0x400E042CU) 45 #define REG_PMC_MCKR (0x400E0430U) 46 #define REG_PMC_USB (0x400E0438U) 47 #define REG_PMC_PCK (0x400E0440U) 48 #define REG_PMC_IER (0x400E0460U) 49 #define REG_PMC_IDR (0x400E0464U) 50 #define REG_PMC_SR (0x400E0468U) 51 #define REG_PMC_IMR (0x400E046CU) 52 #define REG_PMC_FSMR (0x400E0470U) 53 #define REG_PMC_FSPR (0x400E0474U) 54 #define REG_PMC_FOCR (0x400E0478U) 55 #define REG_PMC_WPMR (0x400E04E4U) 56 #define REG_PMC_WPSR (0x400E04E8U) 57 #define REG_PMC_PCER1 (0x400E0500U) 58 #define REG_PMC_PCDR1 (0x400E0504U) 59 #define REG_PMC_PCSR1 (0x400E0508U) 60 #define REG_PMC_OCR (0x400E0510U) 62 #define REG_PMC_SCER (*(WoReg*)0x400E0400U) 63 #define REG_PMC_SCDR (*(WoReg*)0x400E0404U) 64 #define REG_PMC_SCSR (*(RoReg*)0x400E0408U) 65 #define REG_PMC_PCER0 (*(WoReg*)0x400E0410U) 66 #define REG_PMC_PCDR0 (*(WoReg*)0x400E0414U) 67 #define REG_PMC_PCSR0 (*(RoReg*)0x400E0418U) 68 #define REG_CKGR_MOR (*(RwReg*)0x400E0420U) 69 #define REG_CKGR_MCFR (*(RwReg*)0x400E0424U) 70 #define REG_CKGR_PLLAR (*(RwReg*)0x400E0428U) 71 #define REG_CKGR_PLLBR (*(RwReg*)0x400E042CU) 72 #define REG_PMC_MCKR (*(RwReg*)0x400E0430U) 73 #define REG_PMC_USB (*(RwReg*)0x400E0438U) 74 #define REG_PMC_PCK (*(RwReg*)0x400E0440U) 75 #define REG_PMC_IER (*(WoReg*)0x400E0460U) 76 #define REG_PMC_IDR (*(WoReg*)0x400E0464U) 77 #define REG_PMC_SR (*(RoReg*)0x400E0468U) 78 #define REG_PMC_IMR (*(RoReg*)0x400E046CU) 79 #define REG_PMC_FSMR (*(RwReg*)0x400E0470U) 80 #define REG_PMC_FSPR (*(RwReg*)0x400E0474U) 81 #define REG_PMC_FOCR (*(WoReg*)0x400E0478U) 82 #define REG_PMC_WPMR (*(RwReg*)0x400E04E4U) 83 #define REG_PMC_WPSR (*(RoReg*)0x400E04E8U) 84 #define REG_PMC_PCER1 (*(WoReg*)0x400E0500U) 85 #define REG_PMC_PCDR1 (*(WoReg*)0x400E0504U) 86 #define REG_PMC_PCSR1 (*(RoReg*)0x400E0508U) 87 #define REG_PMC_OCR (*(RwReg*)0x400E0510U)