Robobo
instance_tc0.h
1 /* ----------------------------------------------------------------------------
2  * SAM Software Package License
3  * ----------------------------------------------------------------------------
4  * Copyright (c) 2012, Atmel Corporation
5  *
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following condition is met:
10  *
11  * - Redistributions of source code must retain the above copyright notice,
12  * this list of conditions and the disclaimer below.
13  *
14  * Atmel's name may not be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
20  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
23  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  * ----------------------------------------------------------------------------
28  */
29 
30 #ifndef _SAM3XA_TC0_INSTANCE_
31 #define _SAM3XA_TC0_INSTANCE_
32 
33 /* ========== Register definition for TC0 peripheral ========== */
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_TC0_CCR0 (0x40080000U)
36 #define REG_TC0_CMR0 (0x40080004U)
37 #define REG_TC0_SMMR0 (0x40080008U)
38 #define REG_TC0_CV0 (0x40080010U)
39 #define REG_TC0_RA0 (0x40080014U)
40 #define REG_TC0_RB0 (0x40080018U)
41 #define REG_TC0_RC0 (0x4008001CU)
42 #define REG_TC0_SR0 (0x40080020U)
43 #define REG_TC0_IER0 (0x40080024U)
44 #define REG_TC0_IDR0 (0x40080028U)
45 #define REG_TC0_IMR0 (0x4008002CU)
46 #define REG_TC0_CCR1 (0x40080040U)
47 #define REG_TC0_CMR1 (0x40080044U)
48 #define REG_TC0_SMMR1 (0x40080048U)
49 #define REG_TC0_CV1 (0x40080050U)
50 #define REG_TC0_RA1 (0x40080054U)
51 #define REG_TC0_RB1 (0x40080058U)
52 #define REG_TC0_RC1 (0x4008005CU)
53 #define REG_TC0_SR1 (0x40080060U)
54 #define REG_TC0_IER1 (0x40080064U)
55 #define REG_TC0_IDR1 (0x40080068U)
56 #define REG_TC0_IMR1 (0x4008006CU)
57 #define REG_TC0_CCR2 (0x40080080U)
58 #define REG_TC0_CMR2 (0x40080084U)
59 #define REG_TC0_SMMR2 (0x40080088U)
60 #define REG_TC0_CV2 (0x40080090U)
61 #define REG_TC0_RA2 (0x40080094U)
62 #define REG_TC0_RB2 (0x40080098U)
63 #define REG_TC0_RC2 (0x4008009CU)
64 #define REG_TC0_SR2 (0x400800A0U)
65 #define REG_TC0_IER2 (0x400800A4U)
66 #define REG_TC0_IDR2 (0x400800A8U)
67 #define REG_TC0_IMR2 (0x400800ACU)
68 #define REG_TC0_BCR (0x400800C0U)
69 #define REG_TC0_BMR (0x400800C4U)
70 #define REG_TC0_QIER (0x400800C8U)
71 #define REG_TC0_QIDR (0x400800CCU)
72 #define REG_TC0_QIMR (0x400800D0U)
73 #define REG_TC0_QISR (0x400800D4U)
74 #define REG_TC0_FMR (0x400800D8U)
75 #define REG_TC0_WPMR (0x400800E4U)
76 #else
77 #define REG_TC0_CCR0 (*(WoReg*)0x40080000U)
78 #define REG_TC0_CMR0 (*(RwReg*)0x40080004U)
79 #define REG_TC0_SMMR0 (*(RwReg*)0x40080008U)
80 #define REG_TC0_CV0 (*(RoReg*)0x40080010U)
81 #define REG_TC0_RA0 (*(RwReg*)0x40080014U)
82 #define REG_TC0_RB0 (*(RwReg*)0x40080018U)
83 #define REG_TC0_RC0 (*(RwReg*)0x4008001CU)
84 #define REG_TC0_SR0 (*(RoReg*)0x40080020U)
85 #define REG_TC0_IER0 (*(WoReg*)0x40080024U)
86 #define REG_TC0_IDR0 (*(WoReg*)0x40080028U)
87 #define REG_TC0_IMR0 (*(RoReg*)0x4008002CU)
88 #define REG_TC0_CCR1 (*(WoReg*)0x40080040U)
89 #define REG_TC0_CMR1 (*(RwReg*)0x40080044U)
90 #define REG_TC0_SMMR1 (*(RwReg*)0x40080048U)
91 #define REG_TC0_CV1 (*(RoReg*)0x40080050U)
92 #define REG_TC0_RA1 (*(RwReg*)0x40080054U)
93 #define REG_TC0_RB1 (*(RwReg*)0x40080058U)
94 #define REG_TC0_RC1 (*(RwReg*)0x4008005CU)
95 #define REG_TC0_SR1 (*(RoReg*)0x40080060U)
96 #define REG_TC0_IER1 (*(WoReg*)0x40080064U)
97 #define REG_TC0_IDR1 (*(WoReg*)0x40080068U)
98 #define REG_TC0_IMR1 (*(RoReg*)0x4008006CU)
99 #define REG_TC0_CCR2 (*(WoReg*)0x40080080U)
100 #define REG_TC0_CMR2 (*(RwReg*)0x40080084U)
101 #define REG_TC0_SMMR2 (*(RwReg*)0x40080088U)
102 #define REG_TC0_CV2 (*(RoReg*)0x40080090U)
103 #define REG_TC0_RA2 (*(RwReg*)0x40080094U)
104 #define REG_TC0_RB2 (*(RwReg*)0x40080098U)
105 #define REG_TC0_RC2 (*(RwReg*)0x4008009CU)
106 #define REG_TC0_SR2 (*(RoReg*)0x400800A0U)
107 #define REG_TC0_IER2 (*(WoReg*)0x400800A4U)
108 #define REG_TC0_IDR2 (*(WoReg*)0x400800A8U)
109 #define REG_TC0_IMR2 (*(RoReg*)0x400800ACU)
110 #define REG_TC0_BCR (*(WoReg*)0x400800C0U)
111 #define REG_TC0_BMR (*(RwReg*)0x400800C4U)
112 #define REG_TC0_QIER (*(WoReg*)0x400800C8U)
113 #define REG_TC0_QIDR (*(WoReg*)0x400800CCU)
114 #define REG_TC0_QIMR (*(RoReg*)0x400800D0U)
115 #define REG_TC0_QISR (*(RoReg*)0x400800D4U)
116 #define REG_TC0_FMR (*(RwReg*)0x400800D8U)
117 #define REG_TC0_WPMR (*(RwReg*)0x400800E4U)
118 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
119 
120 #endif /* _SAM3XA_TC0_INSTANCE_ */