Robobo
instance_twi0.h
1 /* ----------------------------------------------------------------------------
2  * SAM Software Package License
3  * ----------------------------------------------------------------------------
4  * Copyright (c) 2012, Atmel Corporation
5  *
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following condition is met:
10  *
11  * - Redistributions of source code must retain the above copyright notice,
12  * this list of conditions and the disclaimer below.
13  *
14  * Atmel's name may not be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
20  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
23  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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25  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  * ----------------------------------------------------------------------------
28  */
29 
30 #ifndef _SAM3U_TWI0_INSTANCE_
31 #define _SAM3U_TWI0_INSTANCE_
32 
33 /* ========== Register definition for TWI0 peripheral ========== */
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_TWI0_CR (0x40084000U)
36 #define REG_TWI0_MMR (0x40084004U)
37 #define REG_TWI0_SMR (0x40084008U)
38 #define REG_TWI0_IADR (0x4008400CU)
39 #define REG_TWI0_CWGR (0x40084010U)
40 #define REG_TWI0_SR (0x40084020U)
41 #define REG_TWI0_IER (0x40084024U)
42 #define REG_TWI0_IDR (0x40084028U)
43 #define REG_TWI0_IMR (0x4008402CU)
44 #define REG_TWI0_RHR (0x40084030U)
45 #define REG_TWI0_THR (0x40084034U)
46 #define REG_TWI0_RPR (0x40084100U)
47 #define REG_TWI0_RCR (0x40084104U)
48 #define REG_TWI0_TPR (0x40084108U)
49 #define REG_TWI0_TCR (0x4008410CU)
50 #define REG_TWI0_RNPR (0x40084110U)
51 #define REG_TWI0_RNCR (0x40084114U)
52 #define REG_TWI0_TNPR (0x40084118U)
53 #define REG_TWI0_TNCR (0x4008411CU)
54 #define REG_TWI0_PTCR (0x40084120U)
55 #define REG_TWI0_PTSR (0x40084124U)
56 #else
57 #define REG_TWI0_CR (*(WoReg*)0x40084000U)
58 #define REG_TWI0_MMR (*(RwReg*)0x40084004U)
59 #define REG_TWI0_SMR (*(RwReg*)0x40084008U)
60 #define REG_TWI0_IADR (*(RwReg*)0x4008400CU)
61 #define REG_TWI0_CWGR (*(RwReg*)0x40084010U)
62 #define REG_TWI0_SR (*(RoReg*)0x40084020U)
63 #define REG_TWI0_IER (*(WoReg*)0x40084024U)
64 #define REG_TWI0_IDR (*(WoReg*)0x40084028U)
65 #define REG_TWI0_IMR (*(RoReg*)0x4008402CU)
66 #define REG_TWI0_RHR (*(RoReg*)0x40084030U)
67 #define REG_TWI0_THR (*(WoReg*)0x40084034U)
68 #define REG_TWI0_RPR (*(RwReg*)0x40084100U)
69 #define REG_TWI0_RCR (*(RwReg*)0x40084104U)
70 #define REG_TWI0_TPR (*(RwReg*)0x40084108U)
71 #define REG_TWI0_TCR (*(RwReg*)0x4008410CU)
72 #define REG_TWI0_RNPR (*(RwReg*)0x40084110U)
73 #define REG_TWI0_RNCR (*(RwReg*)0x40084114U)
74 #define REG_TWI0_TNPR (*(RwReg*)0x40084118U)
75 #define REG_TWI0_TNCR (*(RwReg*)0x4008411CU)
76 #define REG_TWI0_PTCR (*(WoReg*)0x40084120U)
77 #define REG_TWI0_PTSR (*(RoReg*)0x40084124U)
78 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
79 
80 #endif /* _SAM3U_TWI0_INSTANCE_ */