Robobo
instance_twi1.h
1 /* ----------------------------------------------------------------------------
2  * SAM Software Package License
3  * ----------------------------------------------------------------------------
4  * Copyright (c) 2012, Atmel Corporation
5  *
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following condition is met:
10  *
11  * - Redistributions of source code must retain the above copyright notice,
12  * this list of conditions and the disclaimer below.
13  *
14  * Atmel's name may not be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
20  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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25  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  * ----------------------------------------------------------------------------
28  */
29 
30 #ifndef _SAM3S_TWI1_INSTANCE_
31 #define _SAM3S_TWI1_INSTANCE_
32 
33 /* ========== Register definition for TWI1 peripheral ========== */
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_TWI1_CR (0x4001C000U)
36 #define REG_TWI1_MMR (0x4001C004U)
37 #define REG_TWI1_SMR (0x4001C008U)
38 #define REG_TWI1_IADR (0x4001C00CU)
39 #define REG_TWI1_CWGR (0x4001C010U)
40 #define REG_TWI1_SR (0x4001C020U)
41 #define REG_TWI1_IER (0x4001C024U)
42 #define REG_TWI1_IDR (0x4001C028U)
43 #define REG_TWI1_IMR (0x4001C02CU)
44 #define REG_TWI1_RHR (0x4001C030U)
45 #define REG_TWI1_THR (0x4001C034U)
46 #define REG_TWI1_RPR (0x4001C100U)
47 #define REG_TWI1_RCR (0x4001C104U)
48 #define REG_TWI1_TPR (0x4001C108U)
49 #define REG_TWI1_TCR (0x4001C10CU)
50 #define REG_TWI1_RNPR (0x4001C110U)
51 #define REG_TWI1_RNCR (0x4001C114U)
52 #define REG_TWI1_TNPR (0x4001C118U)
53 #define REG_TWI1_TNCR (0x4001C11CU)
54 #define REG_TWI1_PTCR (0x4001C120U)
55 #define REG_TWI1_PTSR (0x4001C124U)
56 #else
57 #define REG_TWI1_CR (*(WoReg*)0x4001C000U)
58 #define REG_TWI1_MMR (*(RwReg*)0x4001C004U)
59 #define REG_TWI1_SMR (*(RwReg*)0x4001C008U)
60 #define REG_TWI1_IADR (*(RwReg*)0x4001C00CU)
61 #define REG_TWI1_CWGR (*(RwReg*)0x4001C010U)
62 #define REG_TWI1_SR (*(RoReg*)0x4001C020U)
63 #define REG_TWI1_IER (*(WoReg*)0x4001C024U)
64 #define REG_TWI1_IDR (*(WoReg*)0x4001C028U)
65 #define REG_TWI1_IMR (*(RoReg*)0x4001C02CU)
66 #define REG_TWI1_RHR (*(RoReg*)0x4001C030U)
67 #define REG_TWI1_THR (*(WoReg*)0x4001C034U)
68 #define REG_TWI1_RPR (*(RwReg*)0x4001C100U)
69 #define REG_TWI1_RCR (*(RwReg*)0x4001C104U)
70 #define REG_TWI1_TPR (*(RwReg*)0x4001C108U)
71 #define REG_TWI1_TCR (*(RwReg*)0x4001C10CU)
72 #define REG_TWI1_RNPR (*(RwReg*)0x4001C110U)
73 #define REG_TWI1_RNCR (*(RwReg*)0x4001C114U)
74 #define REG_TWI1_TNPR (*(RwReg*)0x4001C118U)
75 #define REG_TWI1_TNCR (*(RwReg*)0x4001C11CU)
76 #define REG_TWI1_PTCR (*(WoReg*)0x4001C120U)
77 #define REG_TWI1_PTSR (*(RoReg*)0x4001C124U)
78 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
79 
80 #endif /* _SAM3S_TWI1_INSTANCE_ */