sam3n1a.h

/* ----------------------------------------------------------------------------
 *         SAM Software Package License
 * ----------------------------------------------------------------------------
 * Copyright (c) 2012, Atmel Corporation
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following condition is met:
 *
 * - Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the disclaimer below.
 *
 * Atmel's name may not be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * ----------------------------------------------------------------------------
 */

#ifndef _SAM3N1A_
#define _SAM3N1A_


#ifdef __cplusplus
 extern "C" {
#endif

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#include <stdint.h>
#ifndef __cplusplus
typedef volatile const uint32_t RoReg; 
#else
typedef volatile       uint32_t RoReg; 
#endif
typedef volatile       uint32_t WoReg; 
typedef volatile       uint32_t RwReg; 
#endif

/* ************************************************************************** */
/*   CMSIS DEFINITIONS FOR SAM3N1A */
/* ************************************************************************** */

typedef enum IRQn
{
/******  Cortex-M3 Processor Exceptions Numbers ******************************/
  NonMaskableInt_IRQn   = -14, 
  MemoryManagement_IRQn = -12, 
  BusFault_IRQn         = -11, 
  UsageFault_IRQn       = -10, 
  SVCall_IRQn           = -5,  
  DebugMonitor_IRQn     = -4,  
  PendSV_IRQn           = -2,  
  SysTick_IRQn          = -1,  
/******  SAM3N1A specific Interrupt Numbers *********************************/

  SUPC_IRQn            =  0, 
  RSTC_IRQn            =  1, 
  RTC_IRQn             =  2, 
  RTT_IRQn             =  3, 
  WDT_IRQn             =  4, 
  PMC_IRQn             =  5, 
  EFC_IRQn             =  6, 
  UART0_IRQn           =  8, 
  UART1_IRQn           =  9, 
  PIOA_IRQn            = 11, 
  PIOB_IRQn            = 12, 
  USART0_IRQn          = 14, 
  TWI0_IRQn            = 19, 
  TWI1_IRQn            = 20, 
  SPI_IRQn             = 21, 
  TC0_IRQn             = 23, 
  TC1_IRQn             = 24, 
  TC2_IRQn             = 25, 
  ADC_IRQn             = 29, 
  DACC_IRQn            = 30, 
  PWM_IRQn             = 31, 
  PERIPH_COUNT_IRQn    = 32  
} IRQn_Type;

typedef struct _DeviceVectors
{
  /* Stack pointer */
  void* pvStack;

  /* Cortex-M handlers */
  void* pfnReset_Handler;
  void* pfnNMI_Handler;
  void* pfnHardFault_Handler;
  void* pfnMemManage_Handler;
  void* pfnBusFault_Handler;
  void* pfnUsageFault_Handler;
  void* pfnReserved1_Handler;
  void* pfnReserved2_Handler;
  void* pfnReserved3_Handler;
  void* pfnReserved4_Handler;
  void* pfnSVC_Handler;
  void* pfnDebugMon_Handler;
  void* pfnReserved5_Handler;
  void* pfnPendSV_Handler;
  void* pfnSysTick_Handler;

  /* Peripheral handlers */
  void* pfnSUPC_Handler;   /*  0 Supply Controller */
  void* pfnRSTC_Handler;   /*  1 Reset Controller */
  void* pfnRTC_Handler;    /*  2 Real Time Clock */
  void* pfnRTT_Handler;    /*  3 Real Time Timer */
  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
  void* pfnPMC_Handler;    /*  5 Power Management Controller */
  void* pfnEFC_Handler;    /*  6 Enhanced Flash Controller */
  void* pvReserved7;
  void* pfnUART0_Handler;  /*  8 UART 0 */
  void* pfnUART1_Handler;  /*  9 UART 1 */
  void* pvReserved10;
  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
  void* pvReserved13;
  void* pfnUSART0_Handler; /* 14 USART 0 */
  void* pvReserved15;
  void* pvReserved16;
  void* pvReserved17;
  void* pvReserved18;
  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
  void* pvReserved22;
  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
  void* pvReserved26;
  void* pvReserved27;
  void* pvReserved28;
  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
} DeviceVectors;

/* Cortex-M3 core handlers */
void Reset_Handler      ( void );
void NMI_Handler        ( void );
void HardFault_Handler  ( void );
void MemManage_Handler  ( void );
void BusFault_Handler   ( void );
void UsageFault_Handler ( void );
void SVC_Handler        ( void );
void DebugMon_Handler   ( void );
void PendSV_Handler     ( void );
void SysTick_Handler    ( void );

/* Peripherals handlers */
void ADC_Handler        ( void );
void DACC_Handler       ( void );
void EFC_Handler        ( void );
void PIOA_Handler       ( void );
void PIOB_Handler       ( void );
void PMC_Handler        ( void );
void PWM_Handler        ( void );
void RSTC_Handler       ( void );
void RTC_Handler        ( void );
void RTT_Handler        ( void );
void SPI_Handler        ( void );
void SUPC_Handler       ( void );
void TC0_Handler        ( void );
void TC1_Handler        ( void );
void TC2_Handler        ( void );
void TWI0_Handler       ( void );
void TWI1_Handler       ( void );
void UART0_Handler      ( void );
void UART1_Handler      ( void );
void USART0_Handler     ( void );
void WDT_Handler        ( void );

#define __CM3_REV              0x0200 
#define __MPU_PRESENT          0      
#define __NVIC_PRIO_BITS       4      
#define __Vendor_SysTickConfig 0      
/*
 * \brief CMSIS includes
 */

#include <core_cm3.h>
#if !defined DONT_USE_CMSIS_INIT
#include "system_sam3n.h"
#endif /* DONT_USE_CMSIS_INIT */

/* ************************************************************************** */
/* ************************************************************************** */

#include "component/component_adc.h"
#include "component/component_chipid.h"
#include "component/component_dacc.h"
#include "component/component_efc.h"
#include "component/component_gpbr.h"
#include "component/component_matrix.h"
#include "component/component_pdc.h"
#include "component/component_pio.h"
#include "component/component_pmc.h"
#include "component/component_pwm.h"
#include "component/component_rstc.h"
#include "component/component_rtc.h"
#include "component/component_rtt.h"
#include "component/component_spi.h"
#include "component/component_supc.h"
#include "component/component_tc.h"
#include "component/component_twi.h"
#include "component/component_uart.h"
#include "component/component_usart.h"
#include "component/component_wdt.h"
/* ************************************************************************** */
/*   REGISTER ACCESS DEFINITIONS FOR SAM3N1A */
/* ************************************************************************** */

#include "instance/instance_spi.h"
#include "instance/instance_tc0.h"
#include "instance/instance_twi0.h"
#include "instance/instance_twi1.h"
#include "instance/instance_pwm.h"
#include "instance/instance_usart0.h"
#include "instance/instance_adc.h"
#include "instance/instance_dacc.h"
#include "instance/instance_matrix.h"
#include "instance/instance_pmc.h"
#include "instance/instance_uart0.h"
#include "instance/instance_chipid.h"
#include "instance/instance_uart1.h"
#include "instance/instance_efc.h"
#include "instance/instance_pioa.h"
#include "instance/instance_piob.h"
#include "instance/instance_rstc.h"
#include "instance/instance_supc.h"
#include "instance/instance_rtt.h"
#include "instance/instance_wdt.h"
#include "instance/instance_rtc.h"
#include "instance/instance_gpbr.h"
/* ************************************************************************** */
/*   PERIPHERAL ID DEFINITIONS FOR SAM3N1A */
/* ************************************************************************** */

#define ID_SUPC   ( 0) 
#define ID_RSTC   ( 1) 
#define ID_RTC    ( 2) 
#define ID_RTT    ( 3) 
#define ID_WDT    ( 4) 
#define ID_PMC    ( 5) 
#define ID_EFC    ( 6) 
#define ID_UART0  ( 8) 
#define ID_UART1  ( 9) 
#define ID_PIOA   (11) 
#define ID_PIOB   (12) 
#define ID_USART0 (14) 
#define ID_TWI0   (19) 
#define ID_TWI1   (20) 
#define ID_SPI    (21) 
#define ID_TC0    (23) 
#define ID_TC1    (24) 
#define ID_TC2    (25) 
#define ID_ADC    (29) 
#define ID_DACC   (30) 
#define ID_PWM    (31) 
#define ID_PERIPH_COUNT (32) 

/* ************************************************************************** */
/*   BASE ADDRESS DEFINITIONS FOR SAM3N1A */
/* ************************************************************************** */

#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define SPI        (0x40008000U) 
#define PDC_SPI    (0x40008100U) 
#define TC0        (0x40010000U) 
#define TWI0       (0x40018000U) 
#define PDC_TWI0   (0x40018100U) 
#define TWI1       (0x4001C000U) 
#define PWM        (0x40020000U) 
#define USART0     (0x40024000U) 
#define PDC_USART0 (0x40024100U) 
#define ADC        (0x40038000U) 
#define PDC_ADC    (0x40038100U) 
#define DACC       (0x4003C000U) 
#define PDC_DACC   (0x4003C100U) 
#define MATRIX     (0x400E0200U) 
#define PMC        (0x400E0400U) 
#define UART0      (0x400E0600U) 
#define PDC_UART0  (0x400E0700U) 
#define CHIPID     (0x400E0740U) 
#define UART1      (0x400E0800U) 
#define EFC        (0x400E0A00U) 
#define PIOA       (0x400E0E00U) 
#define PIOB       (0x400E1000U) 
#define RSTC       (0x400E1400U) 
#define SUPC       (0x400E1410U) 
#define RTT        (0x400E1430U) 
#define WDT        (0x400E1450U) 
#define RTC        (0x400E1460U) 
#define GPBR       (0x400E1490U) 
#else
#define SPI        ((Spi    *)0x40008000U) 
#define PDC_SPI    ((Pdc    *)0x40008100U) 
#define TC0        ((Tc     *)0x40010000U) 
#define TWI0       ((Twi    *)0x40018000U) 
#define PDC_TWI0   ((Pdc    *)0x40018100U) 
#define TWI1       ((Twi    *)0x4001C000U) 
#define PWM        ((Pwm    *)0x40020000U) 
#define USART0     ((Usart  *)0x40024000U) 
#define PDC_USART0 ((Pdc    *)0x40024100U) 
#define ADC        ((Adc    *)0x40038000U) 
#define PDC_ADC    ((Pdc    *)0x40038100U) 
#define DACC       ((Dacc   *)0x4003C000U) 
#define PDC_DACC   ((Pdc    *)0x4003C100U) 
#define MATRIX     ((Matrix *)0x400E0200U) 
#define PMC        ((Pmc    *)0x400E0400U) 
#define UART0      ((Uart   *)0x400E0600U) 
#define PDC_UART0  ((Pdc    *)0x400E0700U) 
#define CHIPID     ((Chipid *)0x400E0740U) 
#define UART1      ((Uart   *)0x400E0800U) 
#define EFC        ((Efc    *)0x400E0A00U) 
#define PIOA       ((Pio    *)0x400E0E00U) 
#define PIOB       ((Pio    *)0x400E1000U) 
#define RSTC       ((Rstc   *)0x400E1400U) 
#define SUPC       ((Supc   *)0x400E1410U) 
#define RTT        ((Rtt    *)0x400E1430U) 
#define WDT        ((Wdt    *)0x400E1450U) 
#define RTC        ((Rtc    *)0x400E1460U) 
#define GPBR       ((Gpbr   *)0x400E1490U) 
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/* ************************************************************************** */
/*   PIO DEFINITIONS FOR SAM3N1A */
/* ************************************************************************** */

#include "pio/pio_sam3n1a.h"
/* ************************************************************************** */
/*   MEMORY MAPPING DEFINITIONS FOR SAM3N1A */
/* ************************************************************************** */

#define IFLASH_SIZE             (0x10000u)
#define IFLASH_PAGE_SIZE        (256u)
#define IFLASH_LOCK_REGION_SIZE (16384u)
#define IFLASH_NB_OF_PAGES      (256u)
#define IFLASH_NB_OF_LOCK_BITS  (4u)
#define IRAM_SIZE               (0x2000u)

#define IFLASH_ADDR (0x00400000u) 
#define IROM_ADDR   (0x00800000u) 
#define IRAM_ADDR   (0x20000000u) 
/* ************************************************************************** */
/*   ELECTRICAL DEFINITIONS FOR SAM3N1A */
/* ************************************************************************** */

/* Device characteristics */
#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
#define CHIP_FREQ_SLCK_RC               (32000UL)
#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
#define CHIP_FREQ_CPU_MAX               (48000000UL)
#define CHIP_FREQ_XTAL_32K              (32768UL)
#define CHIP_FREQ_XTAL_12M              (12000000UL)

/* Embedded Flash Write Wait State */
#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)

/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
#define CHIP_FREQ_FWS_0                 (21000000UL) 
#define CHIP_FREQ_FWS_1                 (32000000UL) 
#define CHIP_FREQ_FWS_2                 (48000000UL) 
#ifdef __cplusplus
}
#endif

#endif /* _SAM3N1A_ */