Robobo
instance_hsmci.h
1 /* ----------------------------------------------------------------------------
2  * SAM Software Package License
3  * ----------------------------------------------------------------------------
4  * Copyright (c) 2012, Atmel Corporation
5  *
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following condition is met:
10  *
11  * - Redistributions of source code must retain the above copyright notice,
12  * this list of conditions and the disclaimer below.
13  *
14  * Atmel's name may not be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
20  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
23  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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25  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  * ----------------------------------------------------------------------------
28  */
29 
30 #ifndef _SAM3U_HSMCI_INSTANCE_
31 #define _SAM3U_HSMCI_INSTANCE_
32 
33 /* ========== Register definition for HSMCI peripheral ========== */
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_HSMCI_CR (0x40000000U)
36 #define REG_HSMCI_MR (0x40000004U)
37 #define REG_HSMCI_DTOR (0x40000008U)
38 #define REG_HSMCI_SDCR (0x4000000CU)
39 #define REG_HSMCI_ARGR (0x40000010U)
40 #define REG_HSMCI_CMDR (0x40000014U)
41 #define REG_HSMCI_BLKR (0x40000018U)
42 #define REG_HSMCI_CSTOR (0x4000001CU)
43 #define REG_HSMCI_RSPR (0x40000020U)
44 #define REG_HSMCI_RDR (0x40000030U)
45 #define REG_HSMCI_TDR (0x40000034U)
46 #define REG_HSMCI_SR (0x40000040U)
47 #define REG_HSMCI_IER (0x40000044U)
48 #define REG_HSMCI_IDR (0x40000048U)
49 #define REG_HSMCI_IMR (0x4000004CU)
50 #define REG_HSMCI_DMA (0x40000050U)
51 #define REG_HSMCI_CFG (0x40000054U)
52 #define REG_HSMCI_WPMR (0x400000E4U)
53 #define REG_HSMCI_WPSR (0x400000E8U)
54 #define REG_HSMCI_FIFO (0x40000200U)
55 #else
56 #define REG_HSMCI_CR (*(WoReg*)0x40000000U)
57 #define REG_HSMCI_MR (*(RwReg*)0x40000004U)
58 #define REG_HSMCI_DTOR (*(RwReg*)0x40000008U)
59 #define REG_HSMCI_SDCR (*(RwReg*)0x4000000CU)
60 #define REG_HSMCI_ARGR (*(RwReg*)0x40000010U)
61 #define REG_HSMCI_CMDR (*(WoReg*)0x40000014U)
62 #define REG_HSMCI_BLKR (*(RwReg*)0x40000018U)
63 #define REG_HSMCI_CSTOR (*(RwReg*)0x4000001CU)
64 #define REG_HSMCI_RSPR (*(RoReg*)0x40000020U)
65 #define REG_HSMCI_RDR (*(RoReg*)0x40000030U)
66 #define REG_HSMCI_TDR (*(WoReg*)0x40000034U)
67 #define REG_HSMCI_SR (*(RoReg*)0x40000040U)
68 #define REG_HSMCI_IER (*(WoReg*)0x40000044U)
69 #define REG_HSMCI_IDR (*(WoReg*)0x40000048U)
70 #define REG_HSMCI_IMR (*(RoReg*)0x4000004CU)
71 #define REG_HSMCI_DMA (*(RwReg*)0x40000050U)
72 #define REG_HSMCI_CFG (*(RwReg*)0x40000054U)
73 #define REG_HSMCI_WPMR (*(RwReg*)0x400000E4U)
74 #define REG_HSMCI_WPSR (*(RoReg*)0x400000E8U)
75 #define REG_HSMCI_FIFO (*(RwReg*)0x40000200U)
76 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
77 
78 #endif /* _SAM3U_HSMCI_INSTANCE_ */