30 #ifndef _SAM3S_SMC_INSTANCE_ 31 #define _SAM3S_SMC_INSTANCE_ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_SMC_SETUP0 (0x400E0000U) 36 #define REG_SMC_PULSE0 (0x400E0004U) 37 #define REG_SMC_CYCLE0 (0x400E0008U) 38 #define REG_SMC_MODE0 (0x400E000CU) 39 #define REG_SMC_SETUP1 (0x400E0010U) 40 #define REG_SMC_PULSE1 (0x400E0014U) 41 #define REG_SMC_CYCLE1 (0x400E0018U) 42 #define REG_SMC_MODE1 (0x400E001CU) 43 #define REG_SMC_SETUP2 (0x400E0020U) 44 #define REG_SMC_PULSE2 (0x400E0024U) 45 #define REG_SMC_CYCLE2 (0x400E0028U) 46 #define REG_SMC_MODE2 (0x400E002CU) 47 #define REG_SMC_SETUP3 (0x400E0030U) 48 #define REG_SMC_PULSE3 (0x400E0034U) 49 #define REG_SMC_CYCLE3 (0x400E0038U) 50 #define REG_SMC_MODE3 (0x400E003CU) 51 #define REG_SMC_SETUP4 (0x400E0040U) 52 #define REG_SMC_PULSE4 (0x400E0044U) 53 #define REG_SMC_CYCLE4 (0x400E0048U) 54 #define REG_SMC_MODE4 (0x400E004CU) 55 #define REG_SMC_OCMS (0x400E0080U) 56 #define REG_SMC_KEY1 (0x400E0084U) 57 #define REG_SMC_KEY2 (0x400E0088U) 58 #define REG_SMC_WPMR (0x400E00E4U) 59 #define REG_SMC_WPSR (0x400E00E8U) 61 #define REG_SMC_SETUP0 (*(RwReg*)0x400E0000U) 62 #define REG_SMC_PULSE0 (*(RwReg*)0x400E0004U) 63 #define REG_SMC_CYCLE0 (*(RwReg*)0x400E0008U) 64 #define REG_SMC_MODE0 (*(RwReg*)0x400E000CU) 65 #define REG_SMC_SETUP1 (*(RwReg*)0x400E0010U) 66 #define REG_SMC_PULSE1 (*(RwReg*)0x400E0014U) 67 #define REG_SMC_CYCLE1 (*(RwReg*)0x400E0018U) 68 #define REG_SMC_MODE1 (*(RwReg*)0x400E001CU) 69 #define REG_SMC_SETUP2 (*(RwReg*)0x400E0020U) 70 #define REG_SMC_PULSE2 (*(RwReg*)0x400E0024U) 71 #define REG_SMC_CYCLE2 (*(RwReg*)0x400E0028U) 72 #define REG_SMC_MODE2 (*(RwReg*)0x400E002CU) 73 #define REG_SMC_SETUP3 (*(RwReg*)0x400E0030U) 74 #define REG_SMC_PULSE3 (*(RwReg*)0x400E0034U) 75 #define REG_SMC_CYCLE3 (*(RwReg*)0x400E0038U) 76 #define REG_SMC_MODE3 (*(RwReg*)0x400E003CU) 77 #define REG_SMC_SETUP4 (*(RwReg*)0x400E0040U) 78 #define REG_SMC_PULSE4 (*(RwReg*)0x400E0044U) 79 #define REG_SMC_CYCLE4 (*(RwReg*)0x400E0048U) 80 #define REG_SMC_MODE4 (*(RwReg*)0x400E004CU) 81 #define REG_SMC_OCMS (*(RwReg*)0x400E0080U) 82 #define REG_SMC_KEY1 (*(WoReg*)0x400E0084U) 83 #define REG_SMC_KEY2 (*(WoReg*)0x400E0088U) 84 #define REG_SMC_WPMR (*(RwReg*)0x400E00E4U) 85 #define REG_SMC_WPSR (*(RoReg*)0x400E00E8U)