Robobo
instance_smc.h
1 /* ----------------------------------------------------------------------------
2  * SAM Software Package License
3  * ----------------------------------------------------------------------------
4  * Copyright (c) 2012, Atmel Corporation
5  *
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following condition is met:
10  *
11  * - Redistributions of source code must retain the above copyright notice,
12  * this list of conditions and the disclaimer below.
13  *
14  * Atmel's name may not be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
20  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
23  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  * ----------------------------------------------------------------------------
28  */
29 
30 #ifndef _SAM3U_SMC_INSTANCE_
31 #define _SAM3U_SMC_INSTANCE_
32 
33 /* ========== Register definition for SMC peripheral ========== */
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_SMC_CFG (0x400E0000U)
36 #define REG_SMC_CTRL (0x400E0004U)
37 #define REG_SMC_SR (0x400E0008U)
38 #define REG_SMC_IER (0x400E000CU)
39 #define REG_SMC_IDR (0x400E0010U)
40 #define REG_SMC_IMR (0x400E0014U)
41 #define REG_SMC_ADDR (0x400E0018U)
42 #define REG_SMC_BANK (0x400E001CU)
43 #define REG_SMC_ECC_CTRL (0x400E0020U)
44 #define REG_SMC_ECC_MD (0x400E0024U)
45 #define REG_SMC_ECC_SR1 (0x400E0028U)
46 #define REG_SMC_ECC_PR0 (0x400E002CU)
47 #define REG_SMC_ECC_PR1 (0x400E0030U)
48 #define REG_SMC_ECC_SR2 (0x400E0034U)
49 #define REG_SMC_ECC_PR2 (0x400E0038U)
50 #define REG_SMC_ECC_PR3 (0x400E003CU)
51 #define REG_SMC_ECC_PR4 (0x400E0040U)
52 #define REG_SMC_ECC_PR5 (0x400E0044U)
53 #define REG_SMC_ECC_PR6 (0x400E0048U)
54 #define REG_SMC_ECC_PR7 (0x400E004CU)
55 #define REG_SMC_ECC_PR8 (0x400E0050U)
56 #define REG_SMC_ECC_PR9 (0x400E0054U)
57 #define REG_SMC_ECC_PR10 (0x400E0058U)
58 #define REG_SMC_ECC_PR11 (0x400E005CU)
59 #define REG_SMC_ECC_PR12 (0x400E0060U)
60 #define REG_SMC_ECC_PR13 (0x400E0064U)
61 #define REG_SMC_ECC_PR14 (0x400E0068U)
62 #define REG_SMC_ECC_PR15 (0x400E006CU)
63 #define REG_SMC_SETUP0 (0x400E0070U)
64 #define REG_SMC_PULSE0 (0x400E0074U)
65 #define REG_SMC_CYCLE0 (0x400E0078U)
66 #define REG_SMC_TIMINGS0 (0x400E007CU)
67 #define REG_SMC_MODE0 (0x400E0080U)
68 #define REG_SMC_SETUP1 (0x400E0084U)
69 #define REG_SMC_PULSE1 (0x400E0088U)
70 #define REG_SMC_CYCLE1 (0x400E008CU)
71 #define REG_SMC_TIMINGS1 (0x400E0090U)
72 #define REG_SMC_MODE1 (0x400E0094U)
73 #define REG_SMC_SETUP2 (0x400E0098U)
74 #define REG_SMC_PULSE2 (0x400E009CU)
75 #define REG_SMC_CYCLE2 (0x400E00A0U)
76 #define REG_SMC_TIMINGS2 (0x400E00A4U)
77 #define REG_SMC_MODE2 (0x400E00A8U)
78 #define REG_SMC_SETUP3 (0x400E00ACU)
79 #define REG_SMC_PULSE3 (0x400E00B0U)
80 #define REG_SMC_CYCLE3 (0x400E00B4U)
81 #define REG_SMC_TIMINGS3 (0x400E00B8U)
82 #define REG_SMC_MODE3 (0x400E00BCU)
83 #define REG_SMC_OCMS (0x400E0110U)
84 #define REG_SMC_KEY1 (0x400E0114U)
85 #define REG_SMC_KEY2 (0x400E0118U)
86 #define REG_SMC_WPCR (0x400E01E4U)
87 #define REG_SMC_WPSR (0x400E01E8U)
88 #else
89 #define REG_SMC_CFG (*(RwReg*)0x400E0000U)
90 #define REG_SMC_CTRL (*(WoReg*)0x400E0004U)
91 #define REG_SMC_SR (*(RoReg*)0x400E0008U)
92 #define REG_SMC_IER (*(WoReg*)0x400E000CU)
93 #define REG_SMC_IDR (*(WoReg*)0x400E0010U)
94 #define REG_SMC_IMR (*(RoReg*)0x400E0014U)
95 #define REG_SMC_ADDR (*(RwReg*)0x400E0018U)
96 #define REG_SMC_BANK (*(RwReg*)0x400E001CU)
97 #define REG_SMC_ECC_CTRL (*(WoReg*)0x400E0020U)
98 #define REG_SMC_ECC_MD (*(RwReg*)0x400E0024U)
99 #define REG_SMC_ECC_SR1 (*(RoReg*)0x400E0028U)
100 #define REG_SMC_ECC_PR0 (*(RoReg*)0x400E002CU)
101 #define REG_SMC_ECC_PR1 (*(RoReg*)0x400E0030U)
102 #define REG_SMC_ECC_SR2 (*(RoReg*)0x400E0034U)
103 #define REG_SMC_ECC_PR2 (*(RoReg*)0x400E0038U)
104 #define REG_SMC_ECC_PR3 (*(RoReg*)0x400E003CU)
105 #define REG_SMC_ECC_PR4 (*(RoReg*)0x400E0040U)
106 #define REG_SMC_ECC_PR5 (*(RoReg*)0x400E0044U)
107 #define REG_SMC_ECC_PR6 (*(RoReg*)0x400E0048U)
108 #define REG_SMC_ECC_PR7 (*(RoReg*)0x400E004CU)
109 #define REG_SMC_ECC_PR8 (*(RoReg*)0x400E0050U)
110 #define REG_SMC_ECC_PR9 (*(RoReg*)0x400E0054U)
111 #define REG_SMC_ECC_PR10 (*(RoReg*)0x400E0058U)
112 #define REG_SMC_ECC_PR11 (*(RoReg*)0x400E005CU)
113 #define REG_SMC_ECC_PR12 (*(RoReg*)0x400E0060U)
114 #define REG_SMC_ECC_PR13 (*(RoReg*)0x400E0064U)
115 #define REG_SMC_ECC_PR14 (*(RoReg*)0x400E0068U)
116 #define REG_SMC_ECC_PR15 (*(RoReg*)0x400E006CU)
117 #define REG_SMC_SETUP0 (*(RwReg*)0x400E0070U)
118 #define REG_SMC_PULSE0 (*(RwReg*)0x400E0074U)
119 #define REG_SMC_CYCLE0 (*(RwReg*)0x400E0078U)
120 #define REG_SMC_TIMINGS0 (*(RwReg*)0x400E007CU)
121 #define REG_SMC_MODE0 (*(RwReg*)0x400E0080U)
122 #define REG_SMC_SETUP1 (*(RwReg*)0x400E0084U)
123 #define REG_SMC_PULSE1 (*(RwReg*)0x400E0088U)
124 #define REG_SMC_CYCLE1 (*(RwReg*)0x400E008CU)
125 #define REG_SMC_TIMINGS1 (*(RwReg*)0x400E0090U)
126 #define REG_SMC_MODE1 (*(RwReg*)0x400E0094U)
127 #define REG_SMC_SETUP2 (*(RwReg*)0x400E0098U)
128 #define REG_SMC_PULSE2 (*(RwReg*)0x400E009CU)
129 #define REG_SMC_CYCLE2 (*(RwReg*)0x400E00A0U)
130 #define REG_SMC_TIMINGS2 (*(RwReg*)0x400E00A4U)
131 #define REG_SMC_MODE2 (*(RwReg*)0x400E00A8U)
132 #define REG_SMC_SETUP3 (*(RwReg*)0x400E00ACU)
133 #define REG_SMC_PULSE3 (*(RwReg*)0x400E00B0U)
134 #define REG_SMC_CYCLE3 (*(RwReg*)0x400E00B4U)
135 #define REG_SMC_TIMINGS3 (*(RwReg*)0x400E00B8U)
136 #define REG_SMC_MODE3 (*(RwReg*)0x400E00BCU)
137 #define REG_SMC_OCMS (*(RwReg*)0x400E0110U)
138 #define REG_SMC_KEY1 (*(WoReg*)0x400E0114U)
139 #define REG_SMC_KEY2 (*(WoReg*)0x400E0118U)
140 #define REG_SMC_WPCR (*(WoReg*)0x400E01E4U)
141 #define REG_SMC_WPSR (*(RoReg*)0x400E01E8U)
142 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
143 
144 #endif /* _SAM3U_SMC_INSTANCE_ */