Robobo
instance_dmac.h
1 /* ----------------------------------------------------------------------------
2  * SAM Software Package License
3  * ----------------------------------------------------------------------------
4  * Copyright (c) 2012, Atmel Corporation
5  *
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following condition is met:
10  *
11  * - Redistributions of source code must retain the above copyright notice,
12  * this list of conditions and the disclaimer below.
13  *
14  * Atmel's name may not be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
20  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
23  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  * ----------------------------------------------------------------------------
28  */
29 
30 #ifndef _SAM3U_DMAC_INSTANCE_
31 #define _SAM3U_DMAC_INSTANCE_
32 
33 /* ========== Register definition for DMAC peripheral ========== */
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_DMAC_GCFG (0x400B0000U)
36 #define REG_DMAC_EN (0x400B0004U)
37 #define REG_DMAC_SREQ (0x400B0008U)
38 #define REG_DMAC_CREQ (0x400B000CU)
39 #define REG_DMAC_LAST (0x400B0010U)
40 #define REG_DMAC_EBCIER (0x400B0018U)
41 #define REG_DMAC_EBCIDR (0x400B001CU)
42 #define REG_DMAC_EBCIMR (0x400B0020U)
43 #define REG_DMAC_EBCISR (0x400B0024U)
44 #define REG_DMAC_CHER (0x400B0028U)
45 #define REG_DMAC_CHDR (0x400B002CU)
46 #define REG_DMAC_CHSR (0x400B0030U)
47 #define REG_DMAC_SADDR0 (0x400B003CU)
48 #define REG_DMAC_DADDR0 (0x400B0040U)
49 #define REG_DMAC_DSCR0 (0x400B0044U)
50 #define REG_DMAC_CTRLA0 (0x400B0048U)
51 #define REG_DMAC_CTRLB0 (0x400B004CU)
52 #define REG_DMAC_CFG0 (0x400B0050U)
53 #define REG_DMAC_SADDR1 (0x400B0064U)
54 #define REG_DMAC_DADDR1 (0x400B0068U)
55 #define REG_DMAC_DSCR1 (0x400B006CU)
56 #define REG_DMAC_CTRLA1 (0x400B0070U)
57 #define REG_DMAC_CTRLB1 (0x400B0074U)
58 #define REG_DMAC_CFG1 (0x400B0078U)
59 #define REG_DMAC_SADDR2 (0x400B008CU)
60 #define REG_DMAC_DADDR2 (0x400B0090U)
61 #define REG_DMAC_DSCR2 (0x400B0094U)
62 #define REG_DMAC_CTRLA2 (0x400B0098U)
63 #define REG_DMAC_CTRLB2 (0x400B009CU)
64 #define REG_DMAC_CFG2 (0x400B00A0U)
65 #define REG_DMAC_SADDR3 (0x400B00B4U)
66 #define REG_DMAC_DADDR3 (0x400B00B8U)
67 #define REG_DMAC_DSCR3 (0x400B00BCU)
68 #define REG_DMAC_CTRLA3 (0x400B00C0U)
69 #define REG_DMAC_CTRLB3 (0x400B00C4U)
70 #define REG_DMAC_CFG3 (0x400B00C8U)
71 #define REG_DMAC_WPMR (0x400B01E4U)
72 #define REG_DMAC_WPSR (0x400B01E8U)
73 #else
74 #define REG_DMAC_GCFG (*(RwReg*)0x400B0000U)
75 #define REG_DMAC_EN (*(RwReg*)0x400B0004U)
76 #define REG_DMAC_SREQ (*(RwReg*)0x400B0008U)
77 #define REG_DMAC_CREQ (*(RwReg*)0x400B000CU)
78 #define REG_DMAC_LAST (*(RwReg*)0x400B0010U)
79 #define REG_DMAC_EBCIER (*(WoReg*)0x400B0018U)
80 #define REG_DMAC_EBCIDR (*(WoReg*)0x400B001CU)
81 #define REG_DMAC_EBCIMR (*(RoReg*)0x400B0020U)
82 #define REG_DMAC_EBCISR (*(RoReg*)0x400B0024U)
83 #define REG_DMAC_CHER (*(WoReg*)0x400B0028U)
84 #define REG_DMAC_CHDR (*(WoReg*)0x400B002CU)
85 #define REG_DMAC_CHSR (*(RoReg*)0x400B0030U)
86 #define REG_DMAC_SADDR0 (*(RwReg*)0x400B003CU)
87 #define REG_DMAC_DADDR0 (*(RwReg*)0x400B0040U)
88 #define REG_DMAC_DSCR0 (*(RwReg*)0x400B0044U)
89 #define REG_DMAC_CTRLA0 (*(RwReg*)0x400B0048U)
90 #define REG_DMAC_CTRLB0 (*(RwReg*)0x400B004CU)
91 #define REG_DMAC_CFG0 (*(RwReg*)0x400B0050U)
92 #define REG_DMAC_SADDR1 (*(RwReg*)0x400B0064U)
93 #define REG_DMAC_DADDR1 (*(RwReg*)0x400B0068U)
94 #define REG_DMAC_DSCR1 (*(RwReg*)0x400B006CU)
95 #define REG_DMAC_CTRLA1 (*(RwReg*)0x400B0070U)
96 #define REG_DMAC_CTRLB1 (*(RwReg*)0x400B0074U)
97 #define REG_DMAC_CFG1 (*(RwReg*)0x400B0078U)
98 #define REG_DMAC_SADDR2 (*(RwReg*)0x400B008CU)
99 #define REG_DMAC_DADDR2 (*(RwReg*)0x400B0090U)
100 #define REG_DMAC_DSCR2 (*(RwReg*)0x400B0094U)
101 #define REG_DMAC_CTRLA2 (*(RwReg*)0x400B0098U)
102 #define REG_DMAC_CTRLB2 (*(RwReg*)0x400B009CU)
103 #define REG_DMAC_CFG2 (*(RwReg*)0x400B00A0U)
104 #define REG_DMAC_SADDR3 (*(RwReg*)0x400B00B4U)
105 #define REG_DMAC_DADDR3 (*(RwReg*)0x400B00B8U)
106 #define REG_DMAC_DSCR3 (*(RwReg*)0x400B00BCU)
107 #define REG_DMAC_CTRLA3 (*(RwReg*)0x400B00C0U)
108 #define REG_DMAC_CTRLB3 (*(RwReg*)0x400B00C4U)
109 #define REG_DMAC_CFG3 (*(RwReg*)0x400B00C8U)
110 #define REG_DMAC_WPMR (*(RwReg*)0x400B01E4U)
111 #define REG_DMAC_WPSR (*(RoReg*)0x400B01E8U)
112 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
113 
114 #endif /* _SAM3U_DMAC_INSTANCE_ */