30 #ifndef _SAM3U_UDPHS_INSTANCE_ 31 #define _SAM3U_UDPHS_INSTANCE_ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_UDPHS_CTRL (0x400A4000U) 36 #define REG_UDPHS_FNUM (0x400A4004U) 37 #define REG_UDPHS_IEN (0x400A4010U) 38 #define REG_UDPHS_INTSTA (0x400A4014U) 39 #define REG_UDPHS_CLRINT (0x400A4018U) 40 #define REG_UDPHS_EPTRST (0x400A401CU) 41 #define REG_UDPHS_TST (0x400A40E0U) 42 #define REG_UDPHS_IPNAME1 (0x400A40F0U) 43 #define REG_UDPHS_IPNAME2 (0x400A40F4U) 44 #define REG_UDPHS_IPFEATURES (0x400A40F8U) 45 #define REG_UDPHS_EPTCFG0 (0x400A4100U) 46 #define REG_UDPHS_EPTCTLENB0 (0x400A4104U) 47 #define REG_UDPHS_EPTCTLDIS0 (0x400A4108U) 48 #define REG_UDPHS_EPTCTL0 (0x400A410CU) 49 #define REG_UDPHS_EPTSETSTA0 (0x400A4114U) 50 #define REG_UDPHS_EPTCLRSTA0 (0x400A4118U) 51 #define REG_UDPHS_EPTSTA0 (0x400A411CU) 52 #define REG_UDPHS_EPTCFG1 (0x400A4120U) 53 #define REG_UDPHS_EPTCTLENB1 (0x400A4124U) 54 #define REG_UDPHS_EPTCTLDIS1 (0x400A4128U) 55 #define REG_UDPHS_EPTCTL1 (0x400A412CU) 56 #define REG_UDPHS_EPTSETSTA1 (0x400A4134U) 57 #define REG_UDPHS_EPTCLRSTA1 (0x400A4138U) 58 #define REG_UDPHS_EPTSTA1 (0x400A413CU) 59 #define REG_UDPHS_EPTCFG2 (0x400A4140U) 60 #define REG_UDPHS_EPTCTLENB2 (0x400A4144U) 61 #define REG_UDPHS_EPTCTLDIS2 (0x400A4148U) 62 #define REG_UDPHS_EPTCTL2 (0x400A414CU) 63 #define REG_UDPHS_EPTSETSTA2 (0x400A4154U) 64 #define REG_UDPHS_EPTCLRSTA2 (0x400A4158U) 65 #define REG_UDPHS_EPTSTA2 (0x400A415CU) 66 #define REG_UDPHS_EPTCFG3 (0x400A4160U) 67 #define REG_UDPHS_EPTCTLENB3 (0x400A4164U) 68 #define REG_UDPHS_EPTCTLDIS3 (0x400A4168U) 69 #define REG_UDPHS_EPTCTL3 (0x400A416CU) 70 #define REG_UDPHS_EPTSETSTA3 (0x400A4174U) 71 #define REG_UDPHS_EPTCLRSTA3 (0x400A4178U) 72 #define REG_UDPHS_EPTSTA3 (0x400A417CU) 73 #define REG_UDPHS_EPTCFG4 (0x400A4180U) 74 #define REG_UDPHS_EPTCTLENB4 (0x400A4184U) 75 #define REG_UDPHS_EPTCTLDIS4 (0x400A4188U) 76 #define REG_UDPHS_EPTCTL4 (0x400A418CU) 77 #define REG_UDPHS_EPTSETSTA4 (0x400A4194U) 78 #define REG_UDPHS_EPTCLRSTA4 (0x400A4198U) 79 #define REG_UDPHS_EPTSTA4 (0x400A419CU) 80 #define REG_UDPHS_EPTCFG5 (0x400A41A0U) 81 #define REG_UDPHS_EPTCTLENB5 (0x400A41A4U) 82 #define REG_UDPHS_EPTCTLDIS5 (0x400A41A8U) 83 #define REG_UDPHS_EPTCTL5 (0x400A41ACU) 84 #define REG_UDPHS_EPTSETSTA5 (0x400A41B4U) 85 #define REG_UDPHS_EPTCLRSTA5 (0x400A41B8U) 86 #define REG_UDPHS_EPTSTA5 (0x400A41BCU) 87 #define REG_UDPHS_EPTCFG6 (0x400A41C0U) 88 #define REG_UDPHS_EPTCTLENB6 (0x400A41C4U) 89 #define REG_UDPHS_EPTCTLDIS6 (0x400A41C8U) 90 #define REG_UDPHS_EPTCTL6 (0x400A41CCU) 91 #define REG_UDPHS_EPTSETSTA6 (0x400A41D4U) 92 #define REG_UDPHS_EPTCLRSTA6 (0x400A41D8U) 93 #define REG_UDPHS_EPTSTA6 (0x400A41DCU) 94 #define REG_UDPHS_DMANXTDSC0 (0x400A4300U) 95 #define REG_UDPHS_DMAADDRESS0 (0x400A4304U) 96 #define REG_UDPHS_DMACONTROL0 (0x400A4308U) 97 #define REG_UDPHS_DMASTATUS0 (0x400A430CU) 98 #define REG_UDPHS_DMANXTDSC1 (0x400A4310U) 99 #define REG_UDPHS_DMAADDRESS1 (0x400A4314U) 100 #define REG_UDPHS_DMACONTROL1 (0x400A4318U) 101 #define REG_UDPHS_DMASTATUS1 (0x400A431CU) 102 #define REG_UDPHS_DMANXTDSC2 (0x400A4320U) 103 #define REG_UDPHS_DMAADDRESS2 (0x400A4324U) 104 #define REG_UDPHS_DMACONTROL2 (0x400A4328U) 105 #define REG_UDPHS_DMASTATUS2 (0x400A432CU) 106 #define REG_UDPHS_DMANXTDSC3 (0x400A4330U) 107 #define REG_UDPHS_DMAADDRESS3 (0x400A4334U) 108 #define REG_UDPHS_DMACONTROL3 (0x400A4338U) 109 #define REG_UDPHS_DMASTATUS3 (0x400A433CU) 110 #define REG_UDPHS_DMANXTDSC4 (0x400A4340U) 111 #define REG_UDPHS_DMAADDRESS4 (0x400A4344U) 112 #define REG_UDPHS_DMACONTROL4 (0x400A4348U) 113 #define REG_UDPHS_DMASTATUS4 (0x400A434CU) 114 #define REG_UDPHS_DMANXTDSC5 (0x400A4350U) 115 #define REG_UDPHS_DMAADDRESS5 (0x400A4354U) 116 #define REG_UDPHS_DMACONTROL5 (0x400A4358U) 117 #define REG_UDPHS_DMASTATUS5 (0x400A435CU) 119 #define REG_UDPHS_CTRL (*(RwReg*)0x400A4000U) 120 #define REG_UDPHS_FNUM (*(RoReg*)0x400A4004U) 121 #define REG_UDPHS_IEN (*(RwReg*)0x400A4010U) 122 #define REG_UDPHS_INTSTA (*(RoReg*)0x400A4014U) 123 #define REG_UDPHS_CLRINT (*(WoReg*)0x400A4018U) 124 #define REG_UDPHS_EPTRST (*(WoReg*)0x400A401CU) 125 #define REG_UDPHS_TST (*(RwReg*)0x400A40E0U) 126 #define REG_UDPHS_IPNAME1 (*(RoReg*)0x400A40F0U) 127 #define REG_UDPHS_IPNAME2 (*(RoReg*)0x400A40F4U) 128 #define REG_UDPHS_IPFEATURES (*(RoReg*)0x400A40F8U) 129 #define REG_UDPHS_EPTCFG0 (*(RwReg*)0x400A4100U) 130 #define REG_UDPHS_EPTCTLENB0 (*(WoReg*)0x400A4104U) 131 #define REG_UDPHS_EPTCTLDIS0 (*(WoReg*)0x400A4108U) 132 #define REG_UDPHS_EPTCTL0 (*(RoReg*)0x400A410CU) 133 #define REG_UDPHS_EPTSETSTA0 (*(WoReg*)0x400A4114U) 134 #define REG_UDPHS_EPTCLRSTA0 (*(WoReg*)0x400A4118U) 135 #define REG_UDPHS_EPTSTA0 (*(RoReg*)0x400A411CU) 136 #define REG_UDPHS_EPTCFG1 (*(RwReg*)0x400A4120U) 137 #define REG_UDPHS_EPTCTLENB1 (*(WoReg*)0x400A4124U) 138 #define REG_UDPHS_EPTCTLDIS1 (*(WoReg*)0x400A4128U) 139 #define REG_UDPHS_EPTCTL1 (*(RoReg*)0x400A412CU) 140 #define REG_UDPHS_EPTSETSTA1 (*(WoReg*)0x400A4134U) 141 #define REG_UDPHS_EPTCLRSTA1 (*(WoReg*)0x400A4138U) 142 #define REG_UDPHS_EPTSTA1 (*(RoReg*)0x400A413CU) 143 #define REG_UDPHS_EPTCFG2 (*(RwReg*)0x400A4140U) 144 #define REG_UDPHS_EPTCTLENB2 (*(WoReg*)0x400A4144U) 145 #define REG_UDPHS_EPTCTLDIS2 (*(WoReg*)0x400A4148U) 146 #define REG_UDPHS_EPTCTL2 (*(RoReg*)0x400A414CU) 147 #define REG_UDPHS_EPTSETSTA2 (*(WoReg*)0x400A4154U) 148 #define REG_UDPHS_EPTCLRSTA2 (*(WoReg*)0x400A4158U) 149 #define REG_UDPHS_EPTSTA2 (*(RoReg*)0x400A415CU) 150 #define REG_UDPHS_EPTCFG3 (*(RwReg*)0x400A4160U) 151 #define REG_UDPHS_EPTCTLENB3 (*(WoReg*)0x400A4164U) 152 #define REG_UDPHS_EPTCTLDIS3 (*(WoReg*)0x400A4168U) 153 #define REG_UDPHS_EPTCTL3 (*(RoReg*)0x400A416CU) 154 #define REG_UDPHS_EPTSETSTA3 (*(WoReg*)0x400A4174U) 155 #define REG_UDPHS_EPTCLRSTA3 (*(WoReg*)0x400A4178U) 156 #define REG_UDPHS_EPTSTA3 (*(RoReg*)0x400A417CU) 157 #define REG_UDPHS_EPTCFG4 (*(RwReg*)0x400A4180U) 158 #define REG_UDPHS_EPTCTLENB4 (*(WoReg*)0x400A4184U) 159 #define REG_UDPHS_EPTCTLDIS4 (*(WoReg*)0x400A4188U) 160 #define REG_UDPHS_EPTCTL4 (*(RoReg*)0x400A418CU) 161 #define REG_UDPHS_EPTSETSTA4 (*(WoReg*)0x400A4194U) 162 #define REG_UDPHS_EPTCLRSTA4 (*(WoReg*)0x400A4198U) 163 #define REG_UDPHS_EPTSTA4 (*(RoReg*)0x400A419CU) 164 #define REG_UDPHS_EPTCFG5 (*(RwReg*)0x400A41A0U) 165 #define REG_UDPHS_EPTCTLENB5 (*(WoReg*)0x400A41A4U) 166 #define REG_UDPHS_EPTCTLDIS5 (*(WoReg*)0x400A41A8U) 167 #define REG_UDPHS_EPTCTL5 (*(RoReg*)0x400A41ACU) 168 #define REG_UDPHS_EPTSETSTA5 (*(WoReg*)0x400A41B4U) 169 #define REG_UDPHS_EPTCLRSTA5 (*(WoReg*)0x400A41B8U) 170 #define REG_UDPHS_EPTSTA5 (*(RoReg*)0x400A41BCU) 171 #define REG_UDPHS_EPTCFG6 (*(RwReg*)0x400A41C0U) 172 #define REG_UDPHS_EPTCTLENB6 (*(WoReg*)0x400A41C4U) 173 #define REG_UDPHS_EPTCTLDIS6 (*(WoReg*)0x400A41C8U) 174 #define REG_UDPHS_EPTCTL6 (*(RoReg*)0x400A41CCU) 175 #define REG_UDPHS_EPTSETSTA6 (*(WoReg*)0x400A41D4U) 176 #define REG_UDPHS_EPTCLRSTA6 (*(WoReg*)0x400A41D8U) 177 #define REG_UDPHS_EPTSTA6 (*(RoReg*)0x400A41DCU) 178 #define REG_UDPHS_DMANXTDSC0 (*(RwReg*)0x400A4300U) 179 #define REG_UDPHS_DMAADDRESS0 (*(RwReg*)0x400A4304U) 180 #define REG_UDPHS_DMACONTROL0 (*(RwReg*)0x400A4308U) 181 #define REG_UDPHS_DMASTATUS0 (*(RwReg*)0x400A430CU) 182 #define REG_UDPHS_DMANXTDSC1 (*(RwReg*)0x400A4310U) 183 #define REG_UDPHS_DMAADDRESS1 (*(RwReg*)0x400A4314U) 184 #define REG_UDPHS_DMACONTROL1 (*(RwReg*)0x400A4318U) 185 #define REG_UDPHS_DMASTATUS1 (*(RwReg*)0x400A431CU) 186 #define REG_UDPHS_DMANXTDSC2 (*(RwReg*)0x400A4320U) 187 #define REG_UDPHS_DMAADDRESS2 (*(RwReg*)0x400A4324U) 188 #define REG_UDPHS_DMACONTROL2 (*(RwReg*)0x400A4328U) 189 #define REG_UDPHS_DMASTATUS2 (*(RwReg*)0x400A432CU) 190 #define REG_UDPHS_DMANXTDSC3 (*(RwReg*)0x400A4330U) 191 #define REG_UDPHS_DMAADDRESS3 (*(RwReg*)0x400A4334U) 192 #define REG_UDPHS_DMACONTROL3 (*(RwReg*)0x400A4338U) 193 #define REG_UDPHS_DMASTATUS3 (*(RwReg*)0x400A433CU) 194 #define REG_UDPHS_DMANXTDSC4 (*(RwReg*)0x400A4340U) 195 #define REG_UDPHS_DMAADDRESS4 (*(RwReg*)0x400A4344U) 196 #define REG_UDPHS_DMACONTROL4 (*(RwReg*)0x400A4348U) 197 #define REG_UDPHS_DMASTATUS4 (*(RwReg*)0x400A434CU) 198 #define REG_UDPHS_DMANXTDSC5 (*(RwReg*)0x400A4350U) 199 #define REG_UDPHS_DMAADDRESS5 (*(RwReg*)0x400A4354U) 200 #define REG_UDPHS_DMACONTROL5 (*(RwReg*)0x400A4358U) 201 #define REG_UDPHS_DMASTATUS5 (*(RwReg*)0x400A435CU)