Robobo
instance_can0.h
1 /* ----------------------------------------------------------------------------
2  * SAM Software Package License
3  * ----------------------------------------------------------------------------
4  * Copyright (c) 2012, Atmel Corporation
5  *
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following condition is met:
10  *
11  * - Redistributions of source code must retain the above copyright notice,
12  * this list of conditions and the disclaimer below.
13  *
14  * Atmel's name may not be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
20  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
23  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  * ----------------------------------------------------------------------------
28  */
29 
30 #ifndef _SAM3XA_CAN0_INSTANCE_
31 #define _SAM3XA_CAN0_INSTANCE_
32 
33 /* ========== Register definition for CAN0 peripheral ========== */
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_CAN0_MR (0x400B4000U)
36 #define REG_CAN0_IER (0x400B4004U)
37 #define REG_CAN0_IDR (0x400B4008U)
38 #define REG_CAN0_IMR (0x400B400CU)
39 #define REG_CAN0_SR (0x400B4010U)
40 #define REG_CAN0_BR (0x400B4014U)
41 #define REG_CAN0_TIM (0x400B4018U)
42 #define REG_CAN0_TIMESTP (0x400B401CU)
43 #define REG_CAN0_ECR (0x400B4020U)
44 #define REG_CAN0_TCR (0x400B4024U)
45 #define REG_CAN0_ACR (0x400B4028U)
46 #define REG_CAN0_WPMR (0x400B40E4U)
47 #define REG_CAN0_WPSR (0x400B40E8U)
48 #define REG_CAN0_MMR0 (0x400B4200U)
49 #define REG_CAN0_MAM0 (0x400B4204U)
50 #define REG_CAN0_MID0 (0x400B4208U)
51 #define REG_CAN0_MFID0 (0x400B420CU)
52 #define REG_CAN0_MSR0 (0x400B4210U)
53 #define REG_CAN0_MDL0 (0x400B4214U)
54 #define REG_CAN0_MDH0 (0x400B4218U)
55 #define REG_CAN0_MCR0 (0x400B421CU)
56 #define REG_CAN0_MMR1 (0x400B4220U)
57 #define REG_CAN0_MAM1 (0x400B4224U)
58 #define REG_CAN0_MID1 (0x400B4228U)
59 #define REG_CAN0_MFID1 (0x400B422CU)
60 #define REG_CAN0_MSR1 (0x400B4230U)
61 #define REG_CAN0_MDL1 (0x400B4234U)
62 #define REG_CAN0_MDH1 (0x400B4238U)
63 #define REG_CAN0_MCR1 (0x400B423CU)
64 #define REG_CAN0_MMR2 (0x400B4240U)
65 #define REG_CAN0_MAM2 (0x400B4244U)
66 #define REG_CAN0_MID2 (0x400B4248U)
67 #define REG_CAN0_MFID2 (0x400B424CU)
68 #define REG_CAN0_MSR2 (0x400B4250U)
69 #define REG_CAN0_MDL2 (0x400B4254U)
70 #define REG_CAN0_MDH2 (0x400B4258U)
71 #define REG_CAN0_MCR2 (0x400B425CU)
72 #define REG_CAN0_MMR3 (0x400B4260U)
73 #define REG_CAN0_MAM3 (0x400B4264U)
74 #define REG_CAN0_MID3 (0x400B4268U)
75 #define REG_CAN0_MFID3 (0x400B426CU)
76 #define REG_CAN0_MSR3 (0x400B4270U)
77 #define REG_CAN0_MDL3 (0x400B4274U)
78 #define REG_CAN0_MDH3 (0x400B4278U)
79 #define REG_CAN0_MCR3 (0x400B427CU)
80 #define REG_CAN0_MMR4 (0x400B4280U)
81 #define REG_CAN0_MAM4 (0x400B4284U)
82 #define REG_CAN0_MID4 (0x400B4288U)
83 #define REG_CAN0_MFID4 (0x400B428CU)
84 #define REG_CAN0_MSR4 (0x400B4290U)
85 #define REG_CAN0_MDL4 (0x400B4294U)
86 #define REG_CAN0_MDH4 (0x400B4298U)
87 #define REG_CAN0_MCR4 (0x400B429CU)
88 #define REG_CAN0_MMR5 (0x400B42A0U)
89 #define REG_CAN0_MAM5 (0x400B42A4U)
90 #define REG_CAN0_MID5 (0x400B42A8U)
91 #define REG_CAN0_MFID5 (0x400B42ACU)
92 #define REG_CAN0_MSR5 (0x400B42B0U)
93 #define REG_CAN0_MDL5 (0x400B42B4U)
94 #define REG_CAN0_MDH5 (0x400B42B8U)
95 #define REG_CAN0_MCR5 (0x400B42BCU)
96 #define REG_CAN0_MMR6 (0x400B42C0U)
97 #define REG_CAN0_MAM6 (0x400B42C4U)
98 #define REG_CAN0_MID6 (0x400B42C8U)
99 #define REG_CAN0_MFID6 (0x400B42CCU)
100 #define REG_CAN0_MSR6 (0x400B42D0U)
101 #define REG_CAN0_MDL6 (0x400B42D4U)
102 #define REG_CAN0_MDH6 (0x400B42D8U)
103 #define REG_CAN0_MCR6 (0x400B42DCU)
104 #define REG_CAN0_MMR7 (0x400B42E0U)
105 #define REG_CAN0_MAM7 (0x400B42E4U)
106 #define REG_CAN0_MID7 (0x400B42E8U)
107 #define REG_CAN0_MFID7 (0x400B42ECU)
108 #define REG_CAN0_MSR7 (0x400B42F0U)
109 #define REG_CAN0_MDL7 (0x400B42F4U)
110 #define REG_CAN0_MDH7 (0x400B42F8U)
111 #define REG_CAN0_MCR7 (0x400B42FCU)
112 #else
113 #define REG_CAN0_MR (*(RwReg*)0x400B4000U)
114 #define REG_CAN0_IER (*(WoReg*)0x400B4004U)
115 #define REG_CAN0_IDR (*(WoReg*)0x400B4008U)
116 #define REG_CAN0_IMR (*(RoReg*)0x400B400CU)
117 #define REG_CAN0_SR (*(RoReg*)0x400B4010U)
118 #define REG_CAN0_BR (*(RwReg*)0x400B4014U)
119 #define REG_CAN0_TIM (*(RoReg*)0x400B4018U)
120 #define REG_CAN0_TIMESTP (*(RoReg*)0x400B401CU)
121 #define REG_CAN0_ECR (*(RoReg*)0x400B4020U)
122 #define REG_CAN0_TCR (*(WoReg*)0x400B4024U)
123 #define REG_CAN0_ACR (*(WoReg*)0x400B4028U)
124 #define REG_CAN0_WPMR (*(RwReg*)0x400B40E4U)
125 #define REG_CAN0_WPSR (*(RoReg*)0x400B40E8U)
126 #define REG_CAN0_MMR0 (*(RwReg*)0x400B4200U)
127 #define REG_CAN0_MAM0 (*(RwReg*)0x400B4204U)
128 #define REG_CAN0_MID0 (*(RwReg*)0x400B4208U)
129 #define REG_CAN0_MFID0 (*(RoReg*)0x400B420CU)
130 #define REG_CAN0_MSR0 (*(RoReg*)0x400B4210U)
131 #define REG_CAN0_MDL0 (*(RwReg*)0x400B4214U)
132 #define REG_CAN0_MDH0 (*(RwReg*)0x400B4218U)
133 #define REG_CAN0_MCR0 (*(WoReg*)0x400B421CU)
134 #define REG_CAN0_MMR1 (*(RwReg*)0x400B4220U)
135 #define REG_CAN0_MAM1 (*(RwReg*)0x400B4224U)
136 #define REG_CAN0_MID1 (*(RwReg*)0x400B4228U)
137 #define REG_CAN0_MFID1 (*(RoReg*)0x400B422CU)
138 #define REG_CAN0_MSR1 (*(RoReg*)0x400B4230U)
139 #define REG_CAN0_MDL1 (*(RwReg*)0x400B4234U)
140 #define REG_CAN0_MDH1 (*(RwReg*)0x400B4238U)
141 #define REG_CAN0_MCR1 (*(WoReg*)0x400B423CU)
142 #define REG_CAN0_MMR2 (*(RwReg*)0x400B4240U)
143 #define REG_CAN0_MAM2 (*(RwReg*)0x400B4244U)
144 #define REG_CAN0_MID2 (*(RwReg*)0x400B4248U)
145 #define REG_CAN0_MFID2 (*(RoReg*)0x400B424CU)
146 #define REG_CAN0_MSR2 (*(RoReg*)0x400B4250U)
147 #define REG_CAN0_MDL2 (*(RwReg*)0x400B4254U)
148 #define REG_CAN0_MDH2 (*(RwReg*)0x400B4258U)
149 #define REG_CAN0_MCR2 (*(WoReg*)0x400B425CU)
150 #define REG_CAN0_MMR3 (*(RwReg*)0x400B4260U)
151 #define REG_CAN0_MAM3 (*(RwReg*)0x400B4264U)
152 #define REG_CAN0_MID3 (*(RwReg*)0x400B4268U)
153 #define REG_CAN0_MFID3 (*(RoReg*)0x400B426CU)
154 #define REG_CAN0_MSR3 (*(RoReg*)0x400B4270U)
155 #define REG_CAN0_MDL3 (*(RwReg*)0x400B4274U)
156 #define REG_CAN0_MDH3 (*(RwReg*)0x400B4278U)
157 #define REG_CAN0_MCR3 (*(WoReg*)0x400B427CU)
158 #define REG_CAN0_MMR4 (*(RwReg*)0x400B4280U)
159 #define REG_CAN0_MAM4 (*(RwReg*)0x400B4284U)
160 #define REG_CAN0_MID4 (*(RwReg*)0x400B4288U)
161 #define REG_CAN0_MFID4 (*(RoReg*)0x400B428CU)
162 #define REG_CAN0_MSR4 (*(RoReg*)0x400B4290U)
163 #define REG_CAN0_MDL4 (*(RwReg*)0x400B4294U)
164 #define REG_CAN0_MDH4 (*(RwReg*)0x400B4298U)
165 #define REG_CAN0_MCR4 (*(WoReg*)0x400B429CU)
166 #define REG_CAN0_MMR5 (*(RwReg*)0x400B42A0U)
167 #define REG_CAN0_MAM5 (*(RwReg*)0x400B42A4U)
168 #define REG_CAN0_MID5 (*(RwReg*)0x400B42A8U)
169 #define REG_CAN0_MFID5 (*(RoReg*)0x400B42ACU)
170 #define REG_CAN0_MSR5 (*(RoReg*)0x400B42B0U)
171 #define REG_CAN0_MDL5 (*(RwReg*)0x400B42B4U)
172 #define REG_CAN0_MDH5 (*(RwReg*)0x400B42B8U)
173 #define REG_CAN0_MCR5 (*(WoReg*)0x400B42BCU)
174 #define REG_CAN0_MMR6 (*(RwReg*)0x400B42C0U)
175 #define REG_CAN0_MAM6 (*(RwReg*)0x400B42C4U)
176 #define REG_CAN0_MID6 (*(RwReg*)0x400B42C8U)
177 #define REG_CAN0_MFID6 (*(RoReg*)0x400B42CCU)
178 #define REG_CAN0_MSR6 (*(RoReg*)0x400B42D0U)
179 #define REG_CAN0_MDL6 (*(RwReg*)0x400B42D4U)
180 #define REG_CAN0_MDH6 (*(RwReg*)0x400B42D8U)
181 #define REG_CAN0_MCR6 (*(WoReg*)0x400B42DCU)
182 #define REG_CAN0_MMR7 (*(RwReg*)0x400B42E0U)
183 #define REG_CAN0_MAM7 (*(RwReg*)0x400B42E4U)
184 #define REG_CAN0_MID7 (*(RwReg*)0x400B42E8U)
185 #define REG_CAN0_MFID7 (*(RoReg*)0x400B42ECU)
186 #define REG_CAN0_MSR7 (*(RoReg*)0x400B42F0U)
187 #define REG_CAN0_MDL7 (*(RwReg*)0x400B42F4U)
188 #define REG_CAN0_MDH7 (*(RwReg*)0x400B42F8U)
189 #define REG_CAN0_MCR7 (*(WoReg*)0x400B42FCU)
190 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
191 
192 #endif /* _SAM3XA_CAN0_INSTANCE_ */