Robobo
instance_spi1.h
1 /* ----------------------------------------------------------------------------
2  * SAM Software Package License
3  * ----------------------------------------------------------------------------
4  * Copyright (c) 2012, Atmel Corporation
5  *
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following condition is met:
10  *
11  * - Redistributions of source code must retain the above copyright notice,
12  * this list of conditions and the disclaimer below.
13  *
14  * Atmel's name may not be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
20  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  * ----------------------------------------------------------------------------
28  */
29 
30 #ifndef _SAM3XA_SPI1_INSTANCE_
31 #define _SAM3XA_SPI1_INSTANCE_
32 
33 /* ========== Register definition for SPI1 peripheral ========== */
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_SPI1_CR (0x4000C000U)
36 #define REG_SPI1_MR (0x4000C004U)
37 #define REG_SPI1_RDR (0x4000C008U)
38 #define REG_SPI1_TDR (0x4000C00CU)
39 #define REG_SPI1_SR (0x4000C010U)
40 #define REG_SPI1_IER (0x4000C014U)
41 #define REG_SPI1_IDR (0x4000C018U)
42 #define REG_SPI1_IMR (0x4000C01CU)
43 #define REG_SPI1_CSR (0x4000C030U)
44 #define REG_SPI1_WPMR (0x4000C0E4U)
45 #define REG_SPI1_WPSR (0x4000C0E8U)
46 #else
47 #define REG_SPI1_CR (*(WoReg*)0x4000C000U)
48 #define REG_SPI1_MR (*(RwReg*)0x4000C004U)
49 #define REG_SPI1_RDR (*(RoReg*)0x4000C008U)
50 #define REG_SPI1_TDR (*(WoReg*)0x4000C00CU)
51 #define REG_SPI1_SR (*(RoReg*)0x4000C010U)
52 #define REG_SPI1_IER (*(WoReg*)0x4000C014U)
53 #define REG_SPI1_IDR (*(WoReg*)0x4000C018U)
54 #define REG_SPI1_IMR (*(RoReg*)0x4000C01CU)
55 #define REG_SPI1_CSR (*(RwReg*)0x4000C030U)
56 #define REG_SPI1_WPMR (*(RwReg*)0x4000C0E4U)
57 #define REG_SPI1_WPSR (*(RoReg*)0x4000C0E8U)
58 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
59 
60 #endif /* _SAM3XA_SPI1_INSTANCE_ */