Robobo
instance_uotghs.h
1 /* ----------------------------------------------------------------------------
2  * SAM Software Package License
3  * ----------------------------------------------------------------------------
4  * Copyright (c) 2012, Atmel Corporation
5  *
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following condition is met:
10  *
11  * - Redistributions of source code must retain the above copyright notice,
12  * this list of conditions and the disclaimer below.
13  *
14  * Atmel's name may not be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
20  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
23  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  * ----------------------------------------------------------------------------
28  */
29 
30 #ifndef _SAM3XA_UOTGHS_INSTANCE_
31 #define _SAM3XA_UOTGHS_INSTANCE_
32 
33 /* ========== Register definition for UOTGHS peripheral ========== */
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_UOTGHS_DEVCTRL (0x400AC000U)
36 #define REG_UOTGHS_DEVISR (0x400AC004U)
37 #define REG_UOTGHS_DEVICR (0x400AC008U)
38 #define REG_UOTGHS_DEVIFR (0x400AC00CU)
39 #define REG_UOTGHS_DEVIMR (0x400AC010U)
40 #define REG_UOTGHS_DEVIDR (0x400AC014U)
41 #define REG_UOTGHS_DEVIER (0x400AC018U)
42 #define REG_UOTGHS_DEVEPT (0x400AC01CU)
43 #define REG_UOTGHS_DEVFNUM (0x400AC020U)
44 #define REG_UOTGHS_DEVEPTCFG (0x400AC100U)
45 #define REG_UOTGHS_DEVEPTISR (0x400AC130U)
46 #define REG_UOTGHS_DEVEPTICR (0x400AC160U)
47 #define REG_UOTGHS_DEVEPTIFR (0x400AC190U)
48 #define REG_UOTGHS_DEVEPTIMR (0x400AC1C0U)
49 #define REG_UOTGHS_DEVEPTIER (0x400AC1F0U)
50 #define REG_UOTGHS_DEVEPTIDR (0x400AC220U)
51 #define REG_UOTGHS_DEVDMANXTDSC1 (0x400AC310U)
52 #define REG_UOTGHS_DEVDMAADDRESS1 (0x400AC314U)
53 #define REG_UOTGHS_DEVDMACONTROL1 (0x400AC318U)
54 #define REG_UOTGHS_DEVDMASTATUS1 (0x400AC31CU)
55 #define REG_UOTGHS_DEVDMANXTDSC2 (0x400AC320U)
56 #define REG_UOTGHS_DEVDMAADDRESS2 (0x400AC324U)
57 #define REG_UOTGHS_DEVDMACONTROL2 (0x400AC328U)
58 #define REG_UOTGHS_DEVDMASTATUS2 (0x400AC32CU)
59 #define REG_UOTGHS_DEVDMANXTDSC3 (0x400AC330U)
60 #define REG_UOTGHS_DEVDMAADDRESS3 (0x400AC334U)
61 #define REG_UOTGHS_DEVDMACONTROL3 (0x400AC338U)
62 #define REG_UOTGHS_DEVDMASTATUS3 (0x400AC33CU)
63 #define REG_UOTGHS_DEVDMANXTDSC4 (0x400AC340U)
64 #define REG_UOTGHS_DEVDMAADDRESS4 (0x400AC344U)
65 #define REG_UOTGHS_DEVDMACONTROL4 (0x400AC348U)
66 #define REG_UOTGHS_DEVDMASTATUS4 (0x400AC34CU)
67 #define REG_UOTGHS_DEVDMANXTDSC5 (0x400AC350U)
68 #define REG_UOTGHS_DEVDMAADDRESS5 (0x400AC354U)
69 #define REG_UOTGHS_DEVDMACONTROL5 (0x400AC358U)
70 #define REG_UOTGHS_DEVDMASTATUS5 (0x400AC35CU)
71 #define REG_UOTGHS_DEVDMANXTDSC6 (0x400AC360U)
72 #define REG_UOTGHS_DEVDMAADDRESS6 (0x400AC364U)
73 #define REG_UOTGHS_DEVDMACONTROL6 (0x400AC368U)
74 #define REG_UOTGHS_DEVDMASTATUS6 (0x400AC36CU)
75 #define REG_UOTGHS_DEVDMANXTDSC7 (0x400AC370U)
76 #define REG_UOTGHS_DEVDMAADDRESS7 (0x400AC374U)
77 #define REG_UOTGHS_DEVDMACONTROL7 (0x400AC378U)
78 #define REG_UOTGHS_DEVDMASTATUS7 (0x400AC37CU)
79 #define REG_UOTGHS_HSTCTRL (0x400AC400U)
80 #define REG_UOTGHS_HSTISR (0x400AC404U)
81 #define REG_UOTGHS_HSTICR (0x400AC408U)
82 #define REG_UOTGHS_HSTIFR (0x400AC40CU)
83 #define REG_UOTGHS_HSTIMR (0x400AC410U)
84 #define REG_UOTGHS_HSTIDR (0x400AC414U)
85 #define REG_UOTGHS_HSTIER (0x400AC418U)
86 #define REG_UOTGHS_HSTPIP (0x400AC41CU)
87 #define REG_UOTGHS_HSTFNUM (0x400AC420U)
88 #define REG_UOTGHS_HSTADDR1 (0x400AC424U)
89 #define REG_UOTGHS_HSTADDR2 (0x400AC428U)
90 #define REG_UOTGHS_HSTADDR3 (0x400AC42CU)
91 #define REG_UOTGHS_HSTPIPCFG (0x400AC500U)
92 #define REG_UOTGHS_HSTPIPISR (0x400AC530U)
93 #define REG_UOTGHS_HSTPIPICR (0x400AC560U)
94 #define REG_UOTGHS_HSTPIPIFR (0x400AC590U)
95 #define REG_UOTGHS_HSTPIPIMR (0x400AC5C0U)
96 #define REG_UOTGHS_HSTPIPIER (0x400AC5F0U)
97 #define REG_UOTGHS_HSTPIPIDR (0x400AC620U)
98 #define REG_UOTGHS_HSTPIPINRQ (0x400AC650U)
99 #define REG_UOTGHS_HSTPIPERR (0x400AC680U)
100 #define REG_UOTGHS_HSTDMANXTDSC1 (0x400AC710U)
101 #define REG_UOTGHS_HSTDMAADDRESS1 (0x400AC714U)
102 #define REG_UOTGHS_HSTDMACONTROL1 (0x400AC718U)
103 #define REG_UOTGHS_HSTDMASTATUS1 (0x400AC71CU)
104 #define REG_UOTGHS_HSTDMANXTDSC2 (0x400AC720U)
105 #define REG_UOTGHS_HSTDMAADDRESS2 (0x400AC724U)
106 #define REG_UOTGHS_HSTDMACONTROL2 (0x400AC728U)
107 #define REG_UOTGHS_HSTDMASTATUS2 (0x400AC72CU)
108 #define REG_UOTGHS_HSTDMANXTDSC3 (0x400AC730U)
109 #define REG_UOTGHS_HSTDMAADDRESS3 (0x400AC734U)
110 #define REG_UOTGHS_HSTDMACONTROL3 (0x400AC738U)
111 #define REG_UOTGHS_HSTDMASTATUS3 (0x400AC73CU)
112 #define REG_UOTGHS_HSTDMANXTDSC4 (0x400AC740U)
113 #define REG_UOTGHS_HSTDMAADDRESS4 (0x400AC744U)
114 #define REG_UOTGHS_HSTDMACONTROL4 (0x400AC748U)
115 #define REG_UOTGHS_HSTDMASTATUS4 (0x400AC74CU)
116 #define REG_UOTGHS_HSTDMANXTDSC5 (0x400AC750U)
117 #define REG_UOTGHS_HSTDMAADDRESS5 (0x400AC754U)
118 #define REG_UOTGHS_HSTDMACONTROL5 (0x400AC758U)
119 #define REG_UOTGHS_HSTDMASTATUS5 (0x400AC75CU)
120 #define REG_UOTGHS_HSTDMANXTDSC6 (0x400AC760U)
121 #define REG_UOTGHS_HSTDMAADDRESS6 (0x400AC764U)
122 #define REG_UOTGHS_HSTDMACONTROL6 (0x400AC768U)
123 #define REG_UOTGHS_HSTDMASTATUS6 (0x400AC76CU)
124 #define REG_UOTGHS_HSTDMANXTDSC7 (0x400AC770U)
125 #define REG_UOTGHS_HSTDMAADDRESS7 (0x400AC774U)
126 #define REG_UOTGHS_HSTDMACONTROL7 (0x400AC778U)
127 #define REG_UOTGHS_HSTDMASTATUS7 (0x400AC77CU)
128 #define REG_UOTGHS_CTRL (0x400AC800U)
129 #define REG_UOTGHS_SR (0x400AC804U)
130 #define REG_UOTGHS_SCR (0x400AC808U)
131 #define REG_UOTGHS_SFR (0x400AC80CU)
132 #define REG_UOTGHS_FSM (0x400AC82CU)
133 #else
134 #define REG_UOTGHS_DEVCTRL (*(RwReg*)0x400AC000U)
135 #define REG_UOTGHS_DEVISR (*(RoReg*)0x400AC004U)
136 #define REG_UOTGHS_DEVICR (*(WoReg*)0x400AC008U)
137 #define REG_UOTGHS_DEVIFR (*(WoReg*)0x400AC00CU)
138 #define REG_UOTGHS_DEVIMR (*(RoReg*)0x400AC010U)
139 #define REG_UOTGHS_DEVIDR (*(WoReg*)0x400AC014U)
140 #define REG_UOTGHS_DEVIER (*(WoReg*)0x400AC018U)
141 #define REG_UOTGHS_DEVEPT (*(RwReg*)0x400AC01CU)
142 #define REG_UOTGHS_DEVFNUM (*(RoReg*)0x400AC020U)
143 #define REG_UOTGHS_DEVEPTCFG (*(RwReg*)0x400AC100U)
144 #define REG_UOTGHS_DEVEPTISR (*(RoReg*)0x400AC130U)
145 #define REG_UOTGHS_DEVEPTICR (*(WoReg*)0x400AC160U)
146 #define REG_UOTGHS_DEVEPTIFR (*(WoReg*)0x400AC190U)
147 #define REG_UOTGHS_DEVEPTIMR (*(RoReg*)0x400AC1C0U)
148 #define REG_UOTGHS_DEVEPTIER (*(WoReg*)0x400AC1F0U)
149 #define REG_UOTGHS_DEVEPTIDR (*(WoReg*)0x400AC220U)
150 #define REG_UOTGHS_DEVDMANXTDSC1 (*(RwReg*)0x400AC310U)
151 #define REG_UOTGHS_DEVDMAADDRESS1 (*(RwReg*)0x400AC314U)
152 #define REG_UOTGHS_DEVDMACONTROL1 (*(RwReg*)0x400AC318U)
153 #define REG_UOTGHS_DEVDMASTATUS1 (*(RwReg*)0x400AC31CU)
154 #define REG_UOTGHS_DEVDMANXTDSC2 (*(RwReg*)0x400AC320U)
155 #define REG_UOTGHS_DEVDMAADDRESS2 (*(RwReg*)0x400AC324U)
156 #define REG_UOTGHS_DEVDMACONTROL2 (*(RwReg*)0x400AC328U)
157 #define REG_UOTGHS_DEVDMASTATUS2 (*(RwReg*)0x400AC32CU)
158 #define REG_UOTGHS_DEVDMANXTDSC3 (*(RwReg*)0x400AC330U)
159 #define REG_UOTGHS_DEVDMAADDRESS3 (*(RwReg*)0x400AC334U)
160 #define REG_UOTGHS_DEVDMACONTROL3 (*(RwReg*)0x400AC338U)
161 #define REG_UOTGHS_DEVDMASTATUS3 (*(RwReg*)0x400AC33CU)
162 #define REG_UOTGHS_DEVDMANXTDSC4 (*(RwReg*)0x400AC340U)
163 #define REG_UOTGHS_DEVDMAADDRESS4 (*(RwReg*)0x400AC344U)
164 #define REG_UOTGHS_DEVDMACONTROL4 (*(RwReg*)0x400AC348U)
165 #define REG_UOTGHS_DEVDMASTATUS4 (*(RwReg*)0x400AC34CU)
166 #define REG_UOTGHS_DEVDMANXTDSC5 (*(RwReg*)0x400AC350U)
167 #define REG_UOTGHS_DEVDMAADDRESS5 (*(RwReg*)0x400AC354U)
168 #define REG_UOTGHS_DEVDMACONTROL5 (*(RwReg*)0x400AC358U)
169 #define REG_UOTGHS_DEVDMASTATUS5 (*(RwReg*)0x400AC35CU)
170 #define REG_UOTGHS_DEVDMANXTDSC6 (*(RwReg*)0x400AC360U)
171 #define REG_UOTGHS_DEVDMAADDRESS6 (*(RwReg*)0x400AC364U)
172 #define REG_UOTGHS_DEVDMACONTROL6 (*(RwReg*)0x400AC368U)
173 #define REG_UOTGHS_DEVDMASTATUS6 (*(RwReg*)0x400AC36CU)
174 #define REG_UOTGHS_DEVDMANXTDSC7 (*(RwReg*)0x400AC370U)
175 #define REG_UOTGHS_DEVDMAADDRESS7 (*(RwReg*)0x400AC374U)
176 #define REG_UOTGHS_DEVDMACONTROL7 (*(RwReg*)0x400AC378U)
177 #define REG_UOTGHS_DEVDMASTATUS7 (*(RwReg*)0x400AC37CU)
178 #define REG_UOTGHS_HSTCTRL (*(RwReg*)0x400AC400U)
179 #define REG_UOTGHS_HSTISR (*(RoReg*)0x400AC404U)
180 #define REG_UOTGHS_HSTICR (*(WoReg*)0x400AC408U)
181 #define REG_UOTGHS_HSTIFR (*(WoReg*)0x400AC40CU)
182 #define REG_UOTGHS_HSTIMR (*(RoReg*)0x400AC410U)
183 #define REG_UOTGHS_HSTIDR (*(WoReg*)0x400AC414U)
184 #define REG_UOTGHS_HSTIER (*(WoReg*)0x400AC418U)
185 #define REG_UOTGHS_HSTPIP (*(RwReg*)0x400AC41CU)
186 #define REG_UOTGHS_HSTFNUM (*(RwReg*)0x400AC420U)
187 #define REG_UOTGHS_HSTADDR1 (*(RwReg*)0x400AC424U)
188 #define REG_UOTGHS_HSTADDR2 (*(RwReg*)0x400AC428U)
189 #define REG_UOTGHS_HSTADDR3 (*(RwReg*)0x400AC42CU)
190 #define REG_UOTGHS_HSTPIPCFG (*(RwReg*)0x400AC500U)
191 #define REG_UOTGHS_HSTPIPISR (*(RoReg*)0x400AC530U)
192 #define REG_UOTGHS_HSTPIPICR (*(WoReg*)0x400AC560U)
193 #define REG_UOTGHS_HSTPIPIFR (*(WoReg*)0x400AC590U)
194 #define REG_UOTGHS_HSTPIPIMR (*(RoReg*)0x400AC5C0U)
195 #define REG_UOTGHS_HSTPIPIER (*(WoReg*)0x400AC5F0U)
196 #define REG_UOTGHS_HSTPIPIDR (*(WoReg*)0x400AC620U)
197 #define REG_UOTGHS_HSTPIPINRQ (*(RwReg*)0x400AC650U)
198 #define REG_UOTGHS_HSTPIPERR (*(RwReg*)0x400AC680U)
199 #define REG_UOTGHS_HSTDMANXTDSC1 (*(RwReg*)0x400AC710U)
200 #define REG_UOTGHS_HSTDMAADDRESS1 (*(RwReg*)0x400AC714U)
201 #define REG_UOTGHS_HSTDMACONTROL1 (*(RwReg*)0x400AC718U)
202 #define REG_UOTGHS_HSTDMASTATUS1 (*(RwReg*)0x400AC71CU)
203 #define REG_UOTGHS_HSTDMANXTDSC2 (*(RwReg*)0x400AC720U)
204 #define REG_UOTGHS_HSTDMAADDRESS2 (*(RwReg*)0x400AC724U)
205 #define REG_UOTGHS_HSTDMACONTROL2 (*(RwReg*)0x400AC728U)
206 #define REG_UOTGHS_HSTDMASTATUS2 (*(RwReg*)0x400AC72CU)
207 #define REG_UOTGHS_HSTDMANXTDSC3 (*(RwReg*)0x400AC730U)
208 #define REG_UOTGHS_HSTDMAADDRESS3 (*(RwReg*)0x400AC734U)
209 #define REG_UOTGHS_HSTDMACONTROL3 (*(RwReg*)0x400AC738U)
210 #define REG_UOTGHS_HSTDMASTATUS3 (*(RwReg*)0x400AC73CU)
211 #define REG_UOTGHS_HSTDMANXTDSC4 (*(RwReg*)0x400AC740U)
212 #define REG_UOTGHS_HSTDMAADDRESS4 (*(RwReg*)0x400AC744U)
213 #define REG_UOTGHS_HSTDMACONTROL4 (*(RwReg*)0x400AC748U)
214 #define REG_UOTGHS_HSTDMASTATUS4 (*(RwReg*)0x400AC74CU)
215 #define REG_UOTGHS_HSTDMANXTDSC5 (*(RwReg*)0x400AC750U)
216 #define REG_UOTGHS_HSTDMAADDRESS5 (*(RwReg*)0x400AC754U)
217 #define REG_UOTGHS_HSTDMACONTROL5 (*(RwReg*)0x400AC758U)
218 #define REG_UOTGHS_HSTDMASTATUS5 (*(RwReg*)0x400AC75CU)
219 #define REG_UOTGHS_HSTDMANXTDSC6 (*(RwReg*)0x400AC760U)
220 #define REG_UOTGHS_HSTDMAADDRESS6 (*(RwReg*)0x400AC764U)
221 #define REG_UOTGHS_HSTDMACONTROL6 (*(RwReg*)0x400AC768U)
222 #define REG_UOTGHS_HSTDMASTATUS6 (*(RwReg*)0x400AC76CU)
223 #define REG_UOTGHS_HSTDMANXTDSC7 (*(RwReg*)0x400AC770U)
224 #define REG_UOTGHS_HSTDMAADDRESS7 (*(RwReg*)0x400AC774U)
225 #define REG_UOTGHS_HSTDMACONTROL7 (*(RwReg*)0x400AC778U)
226 #define REG_UOTGHS_HSTDMASTATUS7 (*(RwReg*)0x400AC77CU)
227 #define REG_UOTGHS_CTRL (*(RwReg*)0x400AC800U)
228 #define REG_UOTGHS_SR (*(RoReg*)0x400AC804U)
229 #define REG_UOTGHS_SCR (*(WoReg*)0x400AC808U)
230 #define REG_UOTGHS_SFR (*(WoReg*)0x400AC80CU)
231 #define REG_UOTGHS_FSM (*(RoReg*)0x400AC82CU)
232 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
233 
234 #endif /* _SAM3XA_UOTGHS_INSTANCE_ */