Sdramc hardware registers. More...

Public Attributes
RwReg	SDRAMC_MR
	(Sdramc Offset: 0x00) SDRAMC Mode Register

RwReg	SDRAMC_TR
	(Sdramc Offset: 0x04) SDRAMC Refresh Timer Register

RwReg	SDRAMC_CR
	(Sdramc Offset: 0x08) SDRAMC Configuration Register

RoReg	Reserved1 [1]

RwReg	SDRAMC_LPR
	(Sdramc Offset: 0x10) SDRAMC Low Power Register

WoReg	SDRAMC_IER
	(Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register

WoReg	SDRAMC_IDR
	(Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register

RoReg	SDRAMC_IMR
	(Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register

RoReg	SDRAMC_ISR
	(Sdramc Offset: 0x20) SDRAMC Interrupt Status Register

RwReg	SDRAMC_MDR
	(Sdramc Offset: 0x24) SDRAMC Memory Device Register

RwReg	SDRAMC_CR1
	(Sdramc Offset: 0x28) SDRAMC Configuration Register 1

RwReg	SDRAMC_OCMS
	(Sdramc Offset: 0x2C) SDRAMC OCMS Register 1

Detailed Description

Sdramc hardware registers.

The documentation for this struct was generated from the following file:

Public Attributes