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Smc Struct Reference
Static Memory Controller | Static Memory Controller | Static Memory Controller | Static Memory Controller | Static Memory Controller

Public Attributes

SmcCs_number SMC_CS_NUMBER [SMCCS_NUMBER_NUMBER]
 (Smc Offset: 0x0) CS_number = 0 .. 4 More...
 
RoReg Reserved1 [12]
 
RwReg SMC_OCMS
 (Smc Offset: 0x80) SMC OCMS MODE Register More...
 
WoReg SMC_KEY1
 (Smc Offset: 0x84) SMC OCMS KEY1 Register More...
 
WoReg SMC_KEY2
 (Smc Offset: 0x88) SMC OCMS KEY2 Register More...
 
RoReg Reserved2 [22]
 
RwReg SMC_WPMR
 (Smc Offset: 0xE4) SMC Write Protect Mode Register
 
RoReg SMC_WPSR
 (Smc Offset: 0xE8) SMC Write Protect Status Register More...
 
RwReg SMC_CFG
 (Smc Offset: 0x000) SMC NFC Configuration Register
 
WoReg SMC_CTRL
 (Smc Offset: 0x004) SMC NFC Control Register
 
RoReg SMC_SR
 (Smc Offset: 0x008) SMC NFC Status Register
 
WoReg SMC_IER
 (Smc Offset: 0x00C) SMC NFC Interrupt Enable Register
 
WoReg SMC_IDR
 (Smc Offset: 0x010) SMC NFC Interrupt Disable Register
 
RoReg SMC_IMR
 (Smc Offset: 0x014) SMC NFC Interrupt Mask Register
 
RwReg SMC_ADDR
 (Smc Offset: 0x018) SMC NFC Address Cycle Zero Register
 
RwReg SMC_BANK
 (Smc Offset: 0x01C) SMC Bank Address Register
 
WoReg SMC_ECC_CTRL
 (Smc Offset: 0x020) SMC ECC Control Register
 
RwReg SMC_ECC_MD
 (Smc Offset: 0x024) SMC ECC Mode Register
 
RoReg SMC_ECC_SR1
 (Smc Offset: 0x028) SMC ECC Status 1 Register
 
RoReg SMC_ECC_PR0
 (Smc Offset: 0x02C) SMC ECC Parity 0 Register
 
RoReg SMC_ECC_PR1
 (Smc Offset: 0x030) SMC ECC parity 1 Register
 
RoReg SMC_ECC_SR2
 (Smc Offset: 0x034) SMC ECC status 2 Register
 
RoReg SMC_ECC_PR2
 (Smc Offset: 0x038) SMC ECC parity 2 Register
 
RoReg SMC_ECC_PR3
 (Smc Offset: 0x03C) SMC ECC parity 3 Register
 
RoReg SMC_ECC_PR4
 (Smc Offset: 0x040) SMC ECC parity 4 Register
 
RoReg SMC_ECC_PR5
 (Smc Offset: 0x044) SMC ECC parity 5 Register
 
RoReg SMC_ECC_PR6
 (Smc Offset: 0x048) SMC ECC parity 6 Register
 
RoReg SMC_ECC_PR7
 (Smc Offset: 0x04C) SMC ECC parity 7 Register
 
RoReg SMC_ECC_PR8
 (Smc Offset: 0x050) SMC ECC parity 8 Register
 
RoReg SMC_ECC_PR9
 (Smc Offset: 0x054) SMC ECC parity 9 Register
 
RoReg SMC_ECC_PR10
 (Smc Offset: 0x058) SMC ECC parity 10 Register
 
RoReg SMC_ECC_PR11
 (Smc Offset: 0x05C) SMC ECC parity 11 Register
 
RoReg SMC_ECC_PR12
 (Smc Offset: 0x060) SMC ECC parity 12 Register
 
RoReg SMC_ECC_PR13
 (Smc Offset: 0x064) SMC ECC parity 13 Register
 
RoReg SMC_ECC_PR14
 (Smc Offset: 0x068) SMC ECC parity 14 Register
 
RoReg SMC_ECC_PR15
 (Smc Offset: 0x06C) SMC ECC parity 15 Register
 
WoReg SMC_WPCR
 (Smc Offset: 0x1E4) Write Protection Control Register
 

Member Data Documentation

SmcCs_number Smc::SMC_CS_NUMBER

(Smc Offset: 0x0) CS_number = 0 .. 4

(Smc Offset: 0x70) CS_number = 0 .. 7

(Smc Offset: 0x70) CS_number = 0 .. 3

WoReg Smc::SMC_KEY1

(Smc Offset: 0x84) SMC OCMS KEY1 Register

(Smc Offset: 0x114) SMC OCMS KEY1 Register

WoReg Smc::SMC_KEY2

(Smc Offset: 0x88) SMC OCMS KEY2 Register

(Smc Offset: 0x118) SMC OCMS KEY2 Register

RwReg Smc::SMC_OCMS

(Smc Offset: 0x80) SMC OCMS MODE Register

(Smc Offset: 0x110) SMC OCMS Register

RoReg Smc::SMC_WPSR

(Smc Offset: 0xE8) SMC Write Protect Status Register

(Smc Offset: 0x1E8) Write Protection Status Register

The documentation for this struct was generated from the following file: