Spi hardware registers. More...

Public Attributes
WoReg	SPI_CR
	(Spi Offset: 0x00) Control Register

RwReg	SPI_MR
	(Spi Offset: 0x04) Mode Register

RoReg	SPI_RDR
	(Spi Offset: 0x08) Receive Data Register

WoReg	SPI_TDR
	(Spi Offset: 0x0C) Transmit Data Register

RoReg	SPI_SR
	(Spi Offset: 0x10) Status Register

WoReg	SPI_IER
	(Spi Offset: 0x14) Interrupt Enable Register

WoReg	SPI_IDR
	(Spi Offset: 0x18) Interrupt Disable Register

RoReg	SPI_IMR
	(Spi Offset: 0x1C) Interrupt Mask Register

RoReg	Reserved1 [4]

RwReg	SPI_CSR [4]
	(Spi Offset: 0x30) Chip Select Register

RoReg	Reserved2 [41]

RwReg	SPI_WPMR
	(Spi Offset: 0xE4) Write Protection Control Register

RoReg	SPI_WPSR
	(Spi Offset: 0xE8) Write Protection Status Register

RoReg	Reserved3 [5]

RwReg	SPI_RPR
	(Spi Offset: 0x100) Receive Pointer Register

RwReg	SPI_RCR
	(Spi Offset: 0x104) Receive Counter Register

RwReg	SPI_TPR
	(Spi Offset: 0x108) Transmit Pointer Register

RwReg	SPI_TCR
	(Spi Offset: 0x10C) Transmit Counter Register

RwReg	SPI_RNPR
	(Spi Offset: 0x110) Receive Next Pointer Register

RwReg	SPI_RNCR
	(Spi Offset: 0x114) Receive Next Counter Register

RwReg	SPI_TNPR
	(Spi Offset: 0x118) Transmit Next Pointer Register

RwReg	SPI_TNCR
	(Spi Offset: 0x11C) Transmit Next Counter Register

WoReg	SPI_PTCR
	(Spi Offset: 0x120) Transfer Control Register

RoReg	SPI_PTSR
	(Spi Offset: 0x124) Transfer Status Register

Detailed Description

Spi hardware registers.

The documentation for this struct was generated from the following file:

Public Attributes