Robobo
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Ssc hardware registers. More...
#include <component_ssc.h>
Public Attributes | |
WoReg | SSC_CR |
(Ssc Offset: 0x0) Control Register | |
RwReg | SSC_CMR |
(Ssc Offset: 0x4) Clock Mode Register | |
RoReg | Reserved1 [2] |
RwReg | SSC_RCMR |
(Ssc Offset: 0x10) Receive Clock Mode Register | |
RwReg | SSC_RFMR |
(Ssc Offset: 0x14) Receive Frame Mode Register | |
RwReg | SSC_TCMR |
(Ssc Offset: 0x18) Transmit Clock Mode Register | |
RwReg | SSC_TFMR |
(Ssc Offset: 0x1C) Transmit Frame Mode Register | |
RoReg | SSC_RHR |
(Ssc Offset: 0x20) Receive Holding Register | |
WoReg | SSC_THR |
(Ssc Offset: 0x24) Transmit Holding Register | |
RoReg | Reserved2 [2] |
RoReg | SSC_RSHR |
(Ssc Offset: 0x30) Receive Sync. Holding Register | |
RwReg | SSC_TSHR |
(Ssc Offset: 0x34) Transmit Sync. Holding Register | |
RwReg | SSC_RC0R |
(Ssc Offset: 0x38) Receive Compare 0 Register | |
RwReg | SSC_RC1R |
(Ssc Offset: 0x3C) Receive Compare 1 Register | |
RoReg | SSC_SR |
(Ssc Offset: 0x40) Status Register | |
WoReg | SSC_IER |
(Ssc Offset: 0x44) Interrupt Enable Register | |
WoReg | SSC_IDR |
(Ssc Offset: 0x48) Interrupt Disable Register | |
RoReg | SSC_IMR |
(Ssc Offset: 0x4C) Interrupt Mask Register | |
RoReg | Reserved3 [37] |
RwReg | SSC_WPMR |
(Ssc Offset: 0xE4) Write Protect Mode Register | |
RoReg | SSC_WPSR |
(Ssc Offset: 0xE8) Write Protect Status Register | |
RoReg | Reserved4 [5] |
RwReg | SSC_RPR |
(Ssc Offset: 0x100) Receive Pointer Register | |
RwReg | SSC_RCR |
(Ssc Offset: 0x104) Receive Counter Register | |
RwReg | SSC_TPR |
(Ssc Offset: 0x108) Transmit Pointer Register | |
RwReg | SSC_TCR |
(Ssc Offset: 0x10C) Transmit Counter Register | |
RwReg | SSC_RNPR |
(Ssc Offset: 0x110) Receive Next Pointer Register | |
RwReg | SSC_RNCR |
(Ssc Offset: 0x114) Receive Next Counter Register | |
RwReg | SSC_TNPR |
(Ssc Offset: 0x118) Transmit Next Pointer Register | |
RwReg | SSC_TNCR |
(Ssc Offset: 0x11C) Transmit Next Counter Register | |
WoReg | SSC_PTCR |
(Ssc Offset: 0x120) Transfer Control Register | |
RoReg | SSC_PTSR |
(Ssc Offset: 0x124) Transfer Status Register | |
Ssc hardware registers.