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Robobo
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Public Attributes | |
| RwReg | UOTGHS_DEVCTRL |
| (Uotghs Offset: 0x0000) Device General Control Register | |
| RoReg | UOTGHS_DEVISR |
| (Uotghs Offset: 0x0004) Device Global Interrupt Status Register | |
| WoReg | UOTGHS_DEVICR |
| (Uotghs Offset: 0x0008) Device Global Interrupt Clear Register | |
| WoReg | UOTGHS_DEVIFR |
| (Uotghs Offset: 0x000C) Device Global Interrupt Set Register | |
| RoReg | UOTGHS_DEVIMR |
| (Uotghs Offset: 0x0010) Device Global Interrupt Mask Register | |
| WoReg | UOTGHS_DEVIDR |
| (Uotghs Offset: 0x0014) Device Global Interrupt Disable Register | |
| WoReg | UOTGHS_DEVIER |
| (Uotghs Offset: 0x0018) Device Global Interrupt Enable Register | |
| RwReg | UOTGHS_DEVEPT |
| (Uotghs Offset: 0x001C) Device Endpoint Register | |
| RoReg | UOTGHS_DEVFNUM |
| (Uotghs Offset: 0x0020) Device Frame Number Register | |
| RoReg | Reserved1 [55] |
| RwReg | UOTGHS_DEVEPTCFG [10] |
| (Uotghs Offset: 0x100) Device Endpoint Configuration Register (n = 0) | |
| RoReg | Reserved2 [2] |
| RoReg | UOTGHS_DEVEPTISR [10] |
| (Uotghs Offset: 0x130) Device Endpoint Status Register (n = 0) | |
| RoReg | Reserved3 [2] |
| WoReg | UOTGHS_DEVEPTICR [10] |
| (Uotghs Offset: 0x160) Device Endpoint Clear Register (n = 0) | |
| RoReg | Reserved4 [2] |
| WoReg | UOTGHS_DEVEPTIFR [10] |
| (Uotghs Offset: 0x190) Device Endpoint Set Register (n = 0) | |
| RoReg | Reserved5 [2] |
| RoReg | UOTGHS_DEVEPTIMR [10] |
| (Uotghs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) | |
| RoReg | Reserved6 [2] |
| WoReg | UOTGHS_DEVEPTIER [10] |
| (Uotghs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) | |
| RoReg | Reserved7 [2] |
| WoReg | UOTGHS_DEVEPTIDR [10] |
| (Uotghs Offset: 0x220) Device Endpoint Disable Register (n = 0) | |
| RoReg | Reserved8 [50] |
| UotghsDevdma | UOTGHS_DEVDMA [UOTGHSDEVDMA_NUMBER] |
| (Uotghs Offset: 0x310) n = 1 .. 7 | |
| RoReg | Reserved9 [32] |
| RwReg | UOTGHS_HSTCTRL |
| (Uotghs Offset: 0x0400) Host General Control Register | |
| RoReg | UOTGHS_HSTISR |
| (Uotghs Offset: 0x0404) Host Global Interrupt Status Register | |
| WoReg | UOTGHS_HSTICR |
| (Uotghs Offset: 0x0408) Host Global Interrupt Clear Register | |
| WoReg | UOTGHS_HSTIFR |
| (Uotghs Offset: 0x040C) Host Global Interrupt Set Register | |
| RoReg | UOTGHS_HSTIMR |
| (Uotghs Offset: 0x0410) Host Global Interrupt Mask Register | |
| WoReg | UOTGHS_HSTIDR |
| (Uotghs Offset: 0x0414) Host Global Interrupt Disable Register | |
| WoReg | UOTGHS_HSTIER |
| (Uotghs Offset: 0x0418) Host Global Interrupt Enable Register | |
| RwReg | UOTGHS_HSTPIP |
| (Uotghs Offset: 0x0041C) Host Pipe Register | |
| RwReg | UOTGHS_HSTFNUM |
| (Uotghs Offset: 0x0420) Host Frame Number Register | |
| RwReg | UOTGHS_HSTADDR1 |
| (Uotghs Offset: 0x0424) Host Address 1 Register | |
| RwReg | UOTGHS_HSTADDR2 |
| (Uotghs Offset: 0x0428) Host Address 2 Register | |
| RwReg | UOTGHS_HSTADDR3 |
| (Uotghs Offset: 0x042C) Host Address 3 Register | |
| RoReg | Reserved10 [52] |
| RwReg | UOTGHS_HSTPIPCFG [10] |
| (Uotghs Offset: 0x500) Host Pipe Configuration Register (n = 0) | |
| RoReg | Reserved11 [2] |
| RoReg | UOTGHS_HSTPIPISR [10] |
| (Uotghs Offset: 0x530) Host Pipe Status Register (n = 0) | |
| RoReg | Reserved12 [2] |
| WoReg | UOTGHS_HSTPIPICR [10] |
| (Uotghs Offset: 0x560) Host Pipe Clear Register (n = 0) | |
| RoReg | Reserved13 [2] |
| WoReg | UOTGHS_HSTPIPIFR [10] |
| (Uotghs Offset: 0x590) Host Pipe Set Register (n = 0) | |
| RoReg | Reserved14 [2] |
| RoReg | UOTGHS_HSTPIPIMR [10] |
| (Uotghs Offset: 0x5C0) Host Pipe Mask Register (n = 0) | |
| RoReg | Reserved15 [2] |
| WoReg | UOTGHS_HSTPIPIER [10] |
| (Uotghs Offset: 0x5F0) Host Pipe Enable Register (n = 0) | |
| RoReg | Reserved16 [2] |
| WoReg | UOTGHS_HSTPIPIDR [10] |
| (Uotghs Offset: 0x620) Host Pipe Disable Register (n = 0) | |
| RoReg | Reserved17 [2] |
| RwReg | UOTGHS_HSTPIPINRQ [10] |
| (Uotghs Offset: 0x650) Host Pipe IN Request Register (n = 0) | |
| RoReg | Reserved18 [2] |
| RwReg | UOTGHS_HSTPIPERR [10] |
| (Uotghs Offset: 0x680) Host Pipe Error Register (n = 0) | |
| RoReg | Reserved19 [26] |
| UotghsHstdma | UOTGHS_HSTDMA [UOTGHSHSTDMA_NUMBER] |
| (Uotghs Offset: 0x710) n = 1 .. 7 | |
| RoReg | Reserved20 [32] |
| RwReg | UOTGHS_CTRL |
| (Uotghs Offset: 0x0800) General Control Register | |
| RoReg | UOTGHS_SR |
| (Uotghs Offset: 0x0804) General Status Register | |
| WoReg | UOTGHS_SCR |
| (Uotghs Offset: 0x0808) General Status Clear Register | |
| WoReg | UOTGHS_SFR |
| (Uotghs Offset: 0x080C) General Status Set Register | |
| RoReg | Reserved21 [7] |
| RoReg | UOTGHS_FSM |
| (Uotghs Offset: 0x082C) General Finite State Machine Register | |
1.8.11 
