component_adc.h

/* ----------------------------------------------------------------------------
 *         SAM Software Package License
 * ----------------------------------------------------------------------------
 * Copyright (c) 2012, Atmel Corporation
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following condition is met:
 *
 * - Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the disclaimer below.
 *
 * Atmel's name may not be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * ----------------------------------------------------------------------------
 */

#ifndef _SAM3N_ADC_COMPONENT_
#define _SAM3N_ADC_COMPONENT_

/* ============================================================================= */
/* ============================================================================= */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {
  WoReg ADC_CR;        
  RwReg ADC_MR;        
  RwReg ADC_SEQR1;     
  RwReg ADC_SEQR2;     
  WoReg ADC_CHER;      
  WoReg ADC_CHDR;      
  RoReg ADC_CHSR;      
  RoReg Reserved1[1];
  RoReg ADC_LCDR;      
  WoReg ADC_IER;       
  WoReg ADC_IDR;       
  RoReg ADC_IMR;       
  RoReg ADC_ISR;       
  RoReg Reserved2[2];
  RoReg ADC_OVER;      
  RwReg ADC_EMR;       
  RwReg ADC_CWR;       
  RoReg Reserved3[2];
  RoReg ADC_CDR[16];   
  RoReg Reserved4[21];
  RwReg ADC_WPMR;      
  RoReg ADC_WPSR;      
  RoReg Reserved5[5];
  RwReg ADC_RPR;       
  RwReg ADC_RCR;       
  RoReg Reserved6[2];
  RwReg ADC_RNPR;      
  RwReg ADC_RNCR;      
  RoReg Reserved7[2];
  WoReg ADC_PTCR;      
  RoReg ADC_PTSR;      
} Adc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
#define ADC_CR_SWRST (0x1u << 0) 
#define ADC_CR_START (0x1u << 1) 
/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
#define ADC_MR_TRGEN (0x1u << 0) 
#define   ADC_MR_TRGEN_DIS (0x0u << 0) 
#define   ADC_MR_TRGEN_EN (0x1u << 0) 
#define ADC_MR_TRGSEL_Pos 1
#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) 
#define   ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) 
#define   ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) 
#define   ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) 
#define   ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) 
#define ADC_MR_LOWRES (0x1u << 4) 
#define   ADC_MR_LOWRES_BITS_10 (0x0u << 4) 
#define   ADC_MR_LOWRES_BITS_8 (0x1u << 4) 
#define ADC_MR_SLEEP (0x1u << 5) 
#define   ADC_MR_SLEEP_NORMAL (0x0u << 5) 
#define   ADC_MR_SLEEP_SLEEP (0x1u << 5) 
#define ADC_MR_FWUP (0x1u << 6) 
#define   ADC_MR_FWUP_OFF (0x0u << 6) 
#define   ADC_MR_FWUP_ON (0x1u << 6) 
#define ADC_MR_FREERUN (0x1u << 7) 
#define   ADC_MR_FREERUN_OFF (0x0u << 7) 
#define   ADC_MR_FREERUN_ON (0x1u << 7) 
#define ADC_MR_PRESCAL_Pos 8
#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) 
#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))
#define ADC_MR_STARTUP_Pos 16
#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) 
#define   ADC_MR_STARTUP_SUT0 (0x0u << 16) 
#define   ADC_MR_STARTUP_SUT8 (0x1u << 16) 
#define   ADC_MR_STARTUP_SUT16 (0x2u << 16) 
#define   ADC_MR_STARTUP_SUT24 (0x3u << 16) 
#define   ADC_MR_STARTUP_SUT64 (0x4u << 16) 
#define   ADC_MR_STARTUP_SUT80 (0x5u << 16) 
#define   ADC_MR_STARTUP_SUT96 (0x6u << 16) 
#define   ADC_MR_STARTUP_SUT112 (0x7u << 16) 
#define   ADC_MR_STARTUP_SUT512 (0x8u << 16) 
#define   ADC_MR_STARTUP_SUT576 (0x9u << 16) 
#define   ADC_MR_STARTUP_SUT640 (0xAu << 16) 
#define   ADC_MR_STARTUP_SUT704 (0xBu << 16) 
#define   ADC_MR_STARTUP_SUT768 (0xCu << 16) 
#define   ADC_MR_STARTUP_SUT832 (0xDu << 16) 
#define   ADC_MR_STARTUP_SUT896 (0xEu << 16) 
#define   ADC_MR_STARTUP_SUT960 (0xFu << 16) 
#define ADC_MR_TRACKTIM_Pos 24
#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) 
#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))
#define ADC_MR_USEQ (0x1u << 31) 
#define   ADC_MR_USEQ_NUM_ORDER (0x0u << 31) 
#define   ADC_MR_USEQ_REG_ORDER (0x1u << 31) 
/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */
#define ADC_SEQR1_USCH1_Pos 0
#define ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos) 
#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))
#define ADC_SEQR1_USCH2_Pos 4
#define ADC_SEQR1_USCH2_Msk (0xfu << ADC_SEQR1_USCH2_Pos) 
#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))
#define ADC_SEQR1_USCH3_Pos 8
#define ADC_SEQR1_USCH3_Msk (0xfu << ADC_SEQR1_USCH3_Pos) 
#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))
#define ADC_SEQR1_USCH4_Pos 12
#define ADC_SEQR1_USCH4_Msk (0xfu << ADC_SEQR1_USCH4_Pos) 
#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))
#define ADC_SEQR1_USCH5_Pos 16
#define ADC_SEQR1_USCH5_Msk (0xfu << ADC_SEQR1_USCH5_Pos) 
#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))
#define ADC_SEQR1_USCH6_Pos 20
#define ADC_SEQR1_USCH6_Msk (0xfu << ADC_SEQR1_USCH6_Pos) 
#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))
#define ADC_SEQR1_USCH7_Pos 24
#define ADC_SEQR1_USCH7_Msk (0xfu << ADC_SEQR1_USCH7_Pos) 
#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))
#define ADC_SEQR1_USCH8_Pos 28
#define ADC_SEQR1_USCH8_Msk (0xfu << ADC_SEQR1_USCH8_Pos) 
#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))
/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */
#define ADC_SEQR2_USCH9_Pos 0
#define ADC_SEQR2_USCH9_Msk (0xfu << ADC_SEQR2_USCH9_Pos) 
#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))
#define ADC_SEQR2_USCH10_Pos 4
#define ADC_SEQR2_USCH10_Msk (0xfu << ADC_SEQR2_USCH10_Pos) 
#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))
#define ADC_SEQR2_USCH11_Pos 8
#define ADC_SEQR2_USCH11_Msk (0xfu << ADC_SEQR2_USCH11_Pos) 
#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))
#define ADC_SEQR2_USCH12_Pos 12
#define ADC_SEQR2_USCH12_Msk (0xfu << ADC_SEQR2_USCH12_Pos) 
#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))
#define ADC_SEQR2_USCH13_Pos 16
#define ADC_SEQR2_USCH13_Msk (0xfu << ADC_SEQR2_USCH13_Pos) 
#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))
#define ADC_SEQR2_USCH14_Pos 20
#define ADC_SEQR2_USCH14_Msk (0xfu << ADC_SEQR2_USCH14_Pos) 
#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))
#define ADC_SEQR2_USCH15_Pos 24
#define ADC_SEQR2_USCH15_Msk (0xfu << ADC_SEQR2_USCH15_Pos) 
#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))
#define ADC_SEQR2_USCH16_Pos 28
#define ADC_SEQR2_USCH16_Msk (0xfu << ADC_SEQR2_USCH16_Pos) 
#define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos)))
/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
#define ADC_CHER_CH0 (0x1u << 0) 
#define ADC_CHER_CH1 (0x1u << 1) 
#define ADC_CHER_CH2 (0x1u << 2) 
#define ADC_CHER_CH3 (0x1u << 3) 
#define ADC_CHER_CH4 (0x1u << 4) 
#define ADC_CHER_CH5 (0x1u << 5) 
#define ADC_CHER_CH6 (0x1u << 6) 
#define ADC_CHER_CH7 (0x1u << 7) 
#define ADC_CHER_CH8 (0x1u << 8) 
#define ADC_CHER_CH9 (0x1u << 9) 
#define ADC_CHER_CH10 (0x1u << 10) 
#define ADC_CHER_CH11 (0x1u << 11) 
#define ADC_CHER_CH12 (0x1u << 12) 
#define ADC_CHER_CH13 (0x1u << 13) 
#define ADC_CHER_CH14 (0x1u << 14) 
#define ADC_CHER_CH15 (0x1u << 15) 
/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
#define ADC_CHDR_CH0 (0x1u << 0) 
#define ADC_CHDR_CH1 (0x1u << 1) 
#define ADC_CHDR_CH2 (0x1u << 2) 
#define ADC_CHDR_CH3 (0x1u << 3) 
#define ADC_CHDR_CH4 (0x1u << 4) 
#define ADC_CHDR_CH5 (0x1u << 5) 
#define ADC_CHDR_CH6 (0x1u << 6) 
#define ADC_CHDR_CH7 (0x1u << 7) 
#define ADC_CHDR_CH8 (0x1u << 8) 
#define ADC_CHDR_CH9 (0x1u << 9) 
#define ADC_CHDR_CH10 (0x1u << 10) 
#define ADC_CHDR_CH11 (0x1u << 11) 
#define ADC_CHDR_CH12 (0x1u << 12) 
#define ADC_CHDR_CH13 (0x1u << 13) 
#define ADC_CHDR_CH14 (0x1u << 14) 
#define ADC_CHDR_CH15 (0x1u << 15) 
/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
#define ADC_CHSR_CH0 (0x1u << 0) 
#define ADC_CHSR_CH1 (0x1u << 1) 
#define ADC_CHSR_CH2 (0x1u << 2) 
#define ADC_CHSR_CH3 (0x1u << 3) 
#define ADC_CHSR_CH4 (0x1u << 4) 
#define ADC_CHSR_CH5 (0x1u << 5) 
#define ADC_CHSR_CH6 (0x1u << 6) 
#define ADC_CHSR_CH7 (0x1u << 7) 
#define ADC_CHSR_CH8 (0x1u << 8) 
#define ADC_CHSR_CH9 (0x1u << 9) 
#define ADC_CHSR_CH10 (0x1u << 10) 
#define ADC_CHSR_CH11 (0x1u << 11) 
#define ADC_CHSR_CH12 (0x1u << 12) 
#define ADC_CHSR_CH13 (0x1u << 13) 
#define ADC_CHSR_CH14 (0x1u << 14) 
#define ADC_CHSR_CH15 (0x1u << 15) 
/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
#define ADC_LCDR_LDATA_Pos 0
#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) 
#define ADC_LCDR_CHNB_Pos 12
#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) 
/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
#define ADC_IER_EOC0 (0x1u << 0) 
#define ADC_IER_EOC1 (0x1u << 1) 
#define ADC_IER_EOC2 (0x1u << 2) 
#define ADC_IER_EOC3 (0x1u << 3) 
#define ADC_IER_EOC4 (0x1u << 4) 
#define ADC_IER_EOC5 (0x1u << 5) 
#define ADC_IER_EOC6 (0x1u << 6) 
#define ADC_IER_EOC7 (0x1u << 7) 
#define ADC_IER_EOC8 (0x1u << 8) 
#define ADC_IER_EOC9 (0x1u << 9) 
#define ADC_IER_EOC10 (0x1u << 10) 
#define ADC_IER_EOC11 (0x1u << 11) 
#define ADC_IER_EOC12 (0x1u << 12) 
#define ADC_IER_EOC13 (0x1u << 13) 
#define ADC_IER_EOC14 (0x1u << 14) 
#define ADC_IER_EOC15 (0x1u << 15) 
#define ADC_IER_DRDY (0x1u << 24) 
#define ADC_IER_GOVRE (0x1u << 25) 
#define ADC_IER_COMPE (0x1u << 26) 
#define ADC_IER_ENDRX (0x1u << 27) 
#define ADC_IER_RXBUFF (0x1u << 28) 
/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
#define ADC_IDR_EOC0 (0x1u << 0) 
#define ADC_IDR_EOC1 (0x1u << 1) 
#define ADC_IDR_EOC2 (0x1u << 2) 
#define ADC_IDR_EOC3 (0x1u << 3) 
#define ADC_IDR_EOC4 (0x1u << 4) 
#define ADC_IDR_EOC5 (0x1u << 5) 
#define ADC_IDR_EOC6 (0x1u << 6) 
#define ADC_IDR_EOC7 (0x1u << 7) 
#define ADC_IDR_EOC8 (0x1u << 8) 
#define ADC_IDR_EOC9 (0x1u << 9) 
#define ADC_IDR_EOC10 (0x1u << 10) 
#define ADC_IDR_EOC11 (0x1u << 11) 
#define ADC_IDR_EOC12 (0x1u << 12) 
#define ADC_IDR_EOC13 (0x1u << 13) 
#define ADC_IDR_EOC14 (0x1u << 14) 
#define ADC_IDR_EOC15 (0x1u << 15) 
#define ADC_IDR_DRDY (0x1u << 24) 
#define ADC_IDR_GOVRE (0x1u << 25) 
#define ADC_IDR_COMPE (0x1u << 26) 
#define ADC_IDR_ENDRX (0x1u << 27) 
#define ADC_IDR_RXBUFF (0x1u << 28) 
/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
#define ADC_IMR_EOC0 (0x1u << 0) 
#define ADC_IMR_EOC1 (0x1u << 1) 
#define ADC_IMR_EOC2 (0x1u << 2) 
#define ADC_IMR_EOC3 (0x1u << 3) 
#define ADC_IMR_EOC4 (0x1u << 4) 
#define ADC_IMR_EOC5 (0x1u << 5) 
#define ADC_IMR_EOC6 (0x1u << 6) 
#define ADC_IMR_EOC7 (0x1u << 7) 
#define ADC_IMR_EOC8 (0x1u << 8) 
#define ADC_IMR_EOC9 (0x1u << 9) 
#define ADC_IMR_EOC10 (0x1u << 10) 
#define ADC_IMR_EOC11 (0x1u << 11) 
#define ADC_IMR_EOC12 (0x1u << 12) 
#define ADC_IMR_EOC13 (0x1u << 13) 
#define ADC_IMR_EOC14 (0x1u << 14) 
#define ADC_IMR_EOC15 (0x1u << 15) 
#define ADC_IMR_DRDY (0x1u << 24) 
#define ADC_IMR_GOVRE (0x1u << 25) 
#define ADC_IMR_COMPE (0x1u << 26) 
#define ADC_IMR_ENDRX (0x1u << 27) 
#define ADC_IMR_RXBUFF (0x1u << 28) 
/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */
#define ADC_ISR_EOC0 (0x1u << 0) 
#define ADC_ISR_EOC1 (0x1u << 1) 
#define ADC_ISR_EOC2 (0x1u << 2) 
#define ADC_ISR_EOC3 (0x1u << 3) 
#define ADC_ISR_EOC4 (0x1u << 4) 
#define ADC_ISR_EOC5 (0x1u << 5) 
#define ADC_ISR_EOC6 (0x1u << 6) 
#define ADC_ISR_EOC7 (0x1u << 7) 
#define ADC_ISR_EOC8 (0x1u << 8) 
#define ADC_ISR_EOC9 (0x1u << 9) 
#define ADC_ISR_EOC10 (0x1u << 10) 
#define ADC_ISR_EOC11 (0x1u << 11) 
#define ADC_ISR_EOC12 (0x1u << 12) 
#define ADC_ISR_EOC13 (0x1u << 13) 
#define ADC_ISR_EOC14 (0x1u << 14) 
#define ADC_ISR_EOC15 (0x1u << 15) 
#define ADC_ISR_DRDY (0x1u << 24) 
#define ADC_ISR_GOVRE (0x1u << 25) 
#define ADC_ISR_COMPE (0x1u << 26) 
#define ADC_ISR_ENDRX (0x1u << 27) 
#define ADC_ISR_RXBUFF (0x1u << 28) 
/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */
#define ADC_OVER_OVRE0 (0x1u << 0) 
#define ADC_OVER_OVRE1 (0x1u << 1) 
#define ADC_OVER_OVRE2 (0x1u << 2) 
#define ADC_OVER_OVRE3 (0x1u << 3) 
#define ADC_OVER_OVRE4 (0x1u << 4) 
#define ADC_OVER_OVRE5 (0x1u << 5) 
#define ADC_OVER_OVRE6 (0x1u << 6) 
#define ADC_OVER_OVRE7 (0x1u << 7) 
#define ADC_OVER_OVRE8 (0x1u << 8) 
#define ADC_OVER_OVRE9 (0x1u << 9) 
#define ADC_OVER_OVRE10 (0x1u << 10) 
#define ADC_OVER_OVRE11 (0x1u << 11) 
#define ADC_OVER_OVRE12 (0x1u << 12) 
#define ADC_OVER_OVRE13 (0x1u << 13) 
#define ADC_OVER_OVRE14 (0x1u << 14) 
#define ADC_OVER_OVRE15 (0x1u << 15) 
/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */
#define ADC_EMR_CMPMODE_Pos 0
#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) 
#define   ADC_EMR_CMPMODE_LOW (0x0u << 0) 
#define   ADC_EMR_CMPMODE_HIGH (0x1u << 0) 
#define   ADC_EMR_CMPMODE_IN (0x2u << 0) 
#define   ADC_EMR_CMPMODE_OUT (0x3u << 0) 
#define ADC_EMR_CMPSEL_Pos 4
#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) 
#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))
#define ADC_EMR_CMPALL (0x1u << 9) 
#define ADC_EMR_TAG (0x1u << 24) 
/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */
#define ADC_CWR_LOWTHRES_Pos 0
#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) 
#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))
#define ADC_CWR_HIGHTHRES_Pos 16
#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) 
#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))
/* -------- ADC_CDR[16] : (ADC Offset: 0x50) Channel Data Register -------- */
#define ADC_CDR_DATA_Pos 0
#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) 
/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */
#define ADC_WPMR_WPEN (0x1u << 0) 
#define ADC_WPMR_WPKEY_Pos 8
#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) 
#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))
/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */
#define ADC_WPSR_WPVS (0x1u << 0) 
#define ADC_WPSR_WPVSRC_Pos 8
#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) 
/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
#define ADC_RPR_RXPTR_Pos 0
#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) 
#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))
/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
#define ADC_RCR_RXCTR_Pos 0
#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) 
#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))
/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
#define ADC_RNPR_RXNPTR_Pos 0
#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) 
#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))
/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
#define ADC_RNCR_RXNCTR_Pos 0
#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) 
#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))
/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
#define ADC_PTCR_RXTEN (0x1u << 0) 
#define ADC_PTCR_RXTDIS (0x1u << 1) 
#define ADC_PTCR_TXTEN (0x1u << 8) 
#define ADC_PTCR_TXTDIS (0x1u << 9) 
/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
#define ADC_PTSR_RXTEN (0x1u << 0) 
#define ADC_PTSR_TXTEN (0x1u << 8) 


#endif /* _SAM3N_ADC_COMPONENT_ */