Robobo
component_adc.h
1 /* ----------------------------------------------------------------------------
2  * SAM Software Package License
3  * ----------------------------------------------------------------------------
4  * Copyright (c) 2012, Atmel Corporation
5  *
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following condition is met:
10  *
11  * - Redistributions of source code must retain the above copyright notice,
12  * this list of conditions and the disclaimer below.
13  *
14  * Atmel's name may not be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
20  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
23  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  * ----------------------------------------------------------------------------
28  */
29 
30 #ifndef _SAM3S8_ADC_COMPONENT_
31 #define _SAM3S8_ADC_COMPONENT_
32 
33 /* ============================================================================= */
35 /* ============================================================================= */
38 
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40 
41 typedef struct {
42  WoReg ADC_CR;
43  RwReg ADC_MR;
44  RwReg ADC_SEQR1;
45  RwReg ADC_SEQR2;
46  WoReg ADC_CHER;
47  WoReg ADC_CHDR;
48  RoReg ADC_CHSR;
49  RoReg Reserved1[1];
50  RoReg ADC_LCDR;
51  WoReg ADC_IER;
52  WoReg ADC_IDR;
53  RoReg ADC_IMR;
54  RoReg ADC_ISR;
55  RoReg Reserved2[2];
56  RoReg ADC_OVER;
57  RwReg ADC_EMR;
58  RwReg ADC_CWR;
59  RwReg ADC_CGR;
60  RwReg ADC_COR;
61  RoReg ADC_CDR[15];
62  RoReg Reserved3[2];
63  RwReg ADC_ACR;
64  RoReg Reserved4[19];
65  RwReg ADC_WPMR;
66  RoReg ADC_WPSR;
67  RoReg Reserved5[5];
68  RwReg ADC_RPR;
69  RwReg ADC_RCR;
70  RoReg Reserved6[2];
71  RwReg ADC_RNPR;
72  RwReg ADC_RNCR;
73  RoReg Reserved7[2];
74  WoReg ADC_PTCR;
75  RoReg ADC_PTSR;
76 } Adc;
77 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
78 /* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
79 #define ADC_CR_SWRST (0x1u << 0)
80 #define ADC_CR_START (0x1u << 1)
81 #define ADC_CR_AUTOCAL (0x1u << 3)
82 /* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
83 #define ADC_MR_TRGEN (0x1u << 0)
84 #define ADC_MR_TRGEN_DIS (0x0u << 0)
85 #define ADC_MR_TRGEN_EN (0x1u << 0)
86 #define ADC_MR_TRGSEL_Pos 1
87 #define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos)
88 #define ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1)
89 #define ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1)
90 #define ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1)
91 #define ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1)
92 #define ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1)
93 #define ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1)
94 #define ADC_MR_LOWRES (0x1u << 4)
95 #define ADC_MR_LOWRES_BITS_12 (0x0u << 4)
96 #define ADC_MR_LOWRES_BITS_10 (0x1u << 4)
97 #define ADC_MR_SLEEP (0x1u << 5)
98 #define ADC_MR_SLEEP_NORMAL (0x0u << 5)
99 #define ADC_MR_SLEEP_SLEEP (0x1u << 5)
100 #define ADC_MR_FWUP (0x1u << 6)
101 #define ADC_MR_FWUP_OFF (0x0u << 6)
102 #define ADC_MR_FWUP_ON (0x1u << 6)
103 #define ADC_MR_FREERUN (0x1u << 7)
104 #define ADC_MR_FREERUN_OFF (0x0u << 7)
105 #define ADC_MR_FREERUN_ON (0x1u << 7)
106 #define ADC_MR_PRESCAL_Pos 8
107 #define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos)
108 #define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))
109 #define ADC_MR_STARTUP_Pos 16
110 #define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos)
111 #define ADC_MR_STARTUP_SUT0 (0x0u << 16)
112 #define ADC_MR_STARTUP_SUT8 (0x1u << 16)
113 #define ADC_MR_STARTUP_SUT16 (0x2u << 16)
114 #define ADC_MR_STARTUP_SUT24 (0x3u << 16)
115 #define ADC_MR_STARTUP_SUT64 (0x4u << 16)
116 #define ADC_MR_STARTUP_SUT80 (0x5u << 16)
117 #define ADC_MR_STARTUP_SUT96 (0x6u << 16)
118 #define ADC_MR_STARTUP_SUT112 (0x7u << 16)
119 #define ADC_MR_STARTUP_SUT512 (0x8u << 16)
120 #define ADC_MR_STARTUP_SUT576 (0x9u << 16)
121 #define ADC_MR_STARTUP_SUT640 (0xAu << 16)
122 #define ADC_MR_STARTUP_SUT704 (0xBu << 16)
123 #define ADC_MR_STARTUP_SUT768 (0xCu << 16)
124 #define ADC_MR_STARTUP_SUT832 (0xDu << 16)
125 #define ADC_MR_STARTUP_SUT896 (0xEu << 16)
126 #define ADC_MR_STARTUP_SUT960 (0xFu << 16)
127 #define ADC_MR_SETTLING_Pos 20
128 #define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos)
129 #define ADC_MR_SETTLING_AST3 (0x0u << 20)
130 #define ADC_MR_SETTLING_AST5 (0x1u << 20)
131 #define ADC_MR_SETTLING_AST9 (0x2u << 20)
132 #define ADC_MR_SETTLING_AST17 (0x3u << 20)
133 #define ADC_MR_ANACH (0x1u << 23)
134 #define ADC_MR_ANACH_NONE (0x0u << 23)
135 #define ADC_MR_ANACH_ALLOWED (0x1u << 23)
136 #define ADC_MR_TRACKTIM_Pos 24
137 #define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos)
138 #define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))
139 #define ADC_MR_TRANSFER_Pos 28
140 #define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos)
141 #define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos)))
142 #define ADC_MR_USEQ (0x1u << 31)
143 #define ADC_MR_USEQ_NUM_ORDER (0x0u << 31)
144 #define ADC_MR_USEQ_REG_ORDER (0x1u << 31)
145 /* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */
146 #define ADC_SEQR1_USCH1_Pos 0
147 #define ADC_SEQR1_USCH1_Msk (0x7u << ADC_SEQR1_USCH1_Pos)
148 #define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))
149 #define ADC_SEQR1_USCH2_Pos 4
150 #define ADC_SEQR1_USCH2_Msk (0x7u << ADC_SEQR1_USCH2_Pos)
151 #define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))
152 #define ADC_SEQR1_USCH3_Pos 8
153 #define ADC_SEQR1_USCH3_Msk (0x7u << ADC_SEQR1_USCH3_Pos)
154 #define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))
155 #define ADC_SEQR1_USCH4_Pos 12
156 #define ADC_SEQR1_USCH4_Msk (0x7u << ADC_SEQR1_USCH4_Pos)
157 #define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))
158 #define ADC_SEQR1_USCH5_Pos 16
159 #define ADC_SEQR1_USCH5_Msk (0x7u << ADC_SEQR1_USCH5_Pos)
160 #define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))
161 #define ADC_SEQR1_USCH6_Pos 20
162 #define ADC_SEQR1_USCH6_Msk (0x7u << ADC_SEQR1_USCH6_Pos)
163 #define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))
164 #define ADC_SEQR1_USCH7_Pos 24
165 #define ADC_SEQR1_USCH7_Msk (0x7u << ADC_SEQR1_USCH7_Pos)
166 #define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))
167 #define ADC_SEQR1_USCH8_Pos 28
168 #define ADC_SEQR1_USCH8_Msk (0x7u << ADC_SEQR1_USCH8_Pos)
169 #define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))
170 /* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */
171 #define ADC_SEQR2_USCH9_Pos 0
172 #define ADC_SEQR2_USCH9_Msk (0x7u << ADC_SEQR2_USCH9_Pos)
173 #define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))
174 #define ADC_SEQR2_USCH10_Pos 4
175 #define ADC_SEQR2_USCH10_Msk (0x7u << ADC_SEQR2_USCH10_Pos)
176 #define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))
177 #define ADC_SEQR2_USCH11_Pos 8
178 #define ADC_SEQR2_USCH11_Msk (0x7u << ADC_SEQR2_USCH11_Pos)
179 #define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))
180 #define ADC_SEQR2_USCH12_Pos 12
181 #define ADC_SEQR2_USCH12_Msk (0x7u << ADC_SEQR2_USCH12_Pos)
182 #define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))
183 #define ADC_SEQR2_USCH13_Pos 16
184 #define ADC_SEQR2_USCH13_Msk (0x7u << ADC_SEQR2_USCH13_Pos)
185 #define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))
186 #define ADC_SEQR2_USCH14_Pos 20
187 #define ADC_SEQR2_USCH14_Msk (0x7u << ADC_SEQR2_USCH14_Pos)
188 #define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))
189 #define ADC_SEQR2_USCH15_Pos 24
190 #define ADC_SEQR2_USCH15_Msk (0x7u << ADC_SEQR2_USCH15_Pos)
191 #define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))
192 #define ADC_SEQR2_USCH16_Pos 28
193 #define ADC_SEQR2_USCH16_Msk (0x7u << ADC_SEQR2_USCH16_Pos)
194 #define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos)))
195 /* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
196 #define ADC_CHER_CH0 (0x1u << 0)
197 #define ADC_CHER_CH1 (0x1u << 1)
198 #define ADC_CHER_CH2 (0x1u << 2)
199 #define ADC_CHER_CH3 (0x1u << 3)
200 #define ADC_CHER_CH4 (0x1u << 4)
201 #define ADC_CHER_CH5 (0x1u << 5)
202 #define ADC_CHER_CH6 (0x1u << 6)
203 #define ADC_CHER_CH7 (0x1u << 7)
204 #define ADC_CHER_CH8 (0x1u << 8)
205 #define ADC_CHER_CH9 (0x1u << 9)
206 #define ADC_CHER_CH10 (0x1u << 10)
207 #define ADC_CHER_CH11 (0x1u << 11)
208 #define ADC_CHER_CH12 (0x1u << 12)
209 #define ADC_CHER_CH13 (0x1u << 13)
210 #define ADC_CHER_CH14 (0x1u << 14)
211 #define ADC_CHER_CH15 (0x1u << 15)
212 /* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
213 #define ADC_CHDR_CH0 (0x1u << 0)
214 #define ADC_CHDR_CH1 (0x1u << 1)
215 #define ADC_CHDR_CH2 (0x1u << 2)
216 #define ADC_CHDR_CH3 (0x1u << 3)
217 #define ADC_CHDR_CH4 (0x1u << 4)
218 #define ADC_CHDR_CH5 (0x1u << 5)
219 #define ADC_CHDR_CH6 (0x1u << 6)
220 #define ADC_CHDR_CH7 (0x1u << 7)
221 #define ADC_CHDR_CH8 (0x1u << 8)
222 #define ADC_CHDR_CH9 (0x1u << 9)
223 #define ADC_CHDR_CH10 (0x1u << 10)
224 #define ADC_CHDR_CH11 (0x1u << 11)
225 #define ADC_CHDR_CH12 (0x1u << 12)
226 #define ADC_CHDR_CH13 (0x1u << 13)
227 #define ADC_CHDR_CH14 (0x1u << 14)
228 #define ADC_CHDR_CH15 (0x1u << 15)
229 /* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
230 #define ADC_CHSR_CH0 (0x1u << 0)
231 #define ADC_CHSR_CH1 (0x1u << 1)
232 #define ADC_CHSR_CH2 (0x1u << 2)
233 #define ADC_CHSR_CH3 (0x1u << 3)
234 #define ADC_CHSR_CH4 (0x1u << 4)
235 #define ADC_CHSR_CH5 (0x1u << 5)
236 #define ADC_CHSR_CH6 (0x1u << 6)
237 #define ADC_CHSR_CH7 (0x1u << 7)
238 #define ADC_CHSR_CH8 (0x1u << 8)
239 #define ADC_CHSR_CH9 (0x1u << 9)
240 #define ADC_CHSR_CH10 (0x1u << 10)
241 #define ADC_CHSR_CH11 (0x1u << 11)
242 #define ADC_CHSR_CH12 (0x1u << 12)
243 #define ADC_CHSR_CH13 (0x1u << 13)
244 #define ADC_CHSR_CH14 (0x1u << 14)
245 #define ADC_CHSR_CH15 (0x1u << 15)
246 /* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
247 #define ADC_LCDR_LDATA_Pos 0
248 #define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos)
249 #define ADC_LCDR_CHNB_Pos 12
250 #define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos)
251 /* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
252 #define ADC_IER_EOC0 (0x1u << 0)
253 #define ADC_IER_EOC1 (0x1u << 1)
254 #define ADC_IER_EOC2 (0x1u << 2)
255 #define ADC_IER_EOC3 (0x1u << 3)
256 #define ADC_IER_EOC4 (0x1u << 4)
257 #define ADC_IER_EOC5 (0x1u << 5)
258 #define ADC_IER_EOC6 (0x1u << 6)
259 #define ADC_IER_EOC7 (0x1u << 7)
260 #define ADC_IER_EOC8 (0x1u << 8)
261 #define ADC_IER_EOC9 (0x1u << 9)
262 #define ADC_IER_EOC10 (0x1u << 10)
263 #define ADC_IER_EOC11 (0x1u << 11)
264 #define ADC_IER_EOC12 (0x1u << 12)
265 #define ADC_IER_EOC13 (0x1u << 13)
266 #define ADC_IER_EOC14 (0x1u << 14)
267 #define ADC_IER_EOC15 (0x1u << 15)
268 #define ADC_IER_EOCAL (0x1u << 23)
269 #define ADC_IER_DRDY (0x1u << 24)
270 #define ADC_IER_GOVRE (0x1u << 25)
271 #define ADC_IER_COMPE (0x1u << 26)
272 #define ADC_IER_ENDRX (0x1u << 27)
273 #define ADC_IER_RXBUFF (0x1u << 28)
274 /* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
275 #define ADC_IDR_EOC0 (0x1u << 0)
276 #define ADC_IDR_EOC1 (0x1u << 1)
277 #define ADC_IDR_EOC2 (0x1u << 2)
278 #define ADC_IDR_EOC3 (0x1u << 3)
279 #define ADC_IDR_EOC4 (0x1u << 4)
280 #define ADC_IDR_EOC5 (0x1u << 5)
281 #define ADC_IDR_EOC6 (0x1u << 6)
282 #define ADC_IDR_EOC7 (0x1u << 7)
283 #define ADC_IDR_EOC8 (0x1u << 8)
284 #define ADC_IDR_EOC9 (0x1u << 9)
285 #define ADC_IDR_EOC10 (0x1u << 10)
286 #define ADC_IDR_EOC11 (0x1u << 11)
287 #define ADC_IDR_EOC12 (0x1u << 12)
288 #define ADC_IDR_EOC13 (0x1u << 13)
289 #define ADC_IDR_EOC14 (0x1u << 14)
290 #define ADC_IDR_EOC15 (0x1u << 15)
291 #define ADC_IDR_EOCAL (0x1u << 23)
292 #define ADC_IDR_DRDY (0x1u << 24)
293 #define ADC_IDR_GOVRE (0x1u << 25)
294 #define ADC_IDR_COMPE (0x1u << 26)
295 #define ADC_IDR_ENDRX (0x1u << 27)
296 #define ADC_IDR_RXBUFF (0x1u << 28)
297 /* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
298 #define ADC_IMR_EOC0 (0x1u << 0)
299 #define ADC_IMR_EOC1 (0x1u << 1)
300 #define ADC_IMR_EOC2 (0x1u << 2)
301 #define ADC_IMR_EOC3 (0x1u << 3)
302 #define ADC_IMR_EOC4 (0x1u << 4)
303 #define ADC_IMR_EOC5 (0x1u << 5)
304 #define ADC_IMR_EOC6 (0x1u << 6)
305 #define ADC_IMR_EOC7 (0x1u << 7)
306 #define ADC_IMR_EOC8 (0x1u << 8)
307 #define ADC_IMR_EOC9 (0x1u << 9)
308 #define ADC_IMR_EOC10 (0x1u << 10)
309 #define ADC_IMR_EOC11 (0x1u << 11)
310 #define ADC_IMR_EOC12 (0x1u << 12)
311 #define ADC_IMR_EOC13 (0x1u << 13)
312 #define ADC_IMR_EOC14 (0x1u << 14)
313 #define ADC_IMR_EOC15 (0x1u << 15)
314 #define ADC_IMR_EOCAL (0x1u << 23)
315 #define ADC_IMR_DRDY (0x1u << 24)
316 #define ADC_IMR_GOVRE (0x1u << 25)
317 #define ADC_IMR_COMPE (0x1u << 26)
318 #define ADC_IMR_ENDRX (0x1u << 27)
319 #define ADC_IMR_RXBUFF (0x1u << 28)
320 /* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */
321 #define ADC_ISR_EOC0 (0x1u << 0)
322 #define ADC_ISR_EOC1 (0x1u << 1)
323 #define ADC_ISR_EOC2 (0x1u << 2)
324 #define ADC_ISR_EOC3 (0x1u << 3)
325 #define ADC_ISR_EOC4 (0x1u << 4)
326 #define ADC_ISR_EOC5 (0x1u << 5)
327 #define ADC_ISR_EOC6 (0x1u << 6)
328 #define ADC_ISR_EOC7 (0x1u << 7)
329 #define ADC_ISR_EOC8 (0x1u << 8)
330 #define ADC_ISR_EOC9 (0x1u << 9)
331 #define ADC_ISR_EOC10 (0x1u << 10)
332 #define ADC_ISR_EOC11 (0x1u << 11)
333 #define ADC_ISR_EOC12 (0x1u << 12)
334 #define ADC_ISR_EOC13 (0x1u << 13)
335 #define ADC_ISR_EOC14 (0x1u << 14)
336 #define ADC_ISR_EOC15 (0x1u << 15)
337 #define ADC_ISR_EOCAL (0x1u << 23)
338 #define ADC_ISR_DRDY (0x1u << 24)
339 #define ADC_ISR_GOVRE (0x1u << 25)
340 #define ADC_ISR_COMPE (0x1u << 26)
341 #define ADC_ISR_ENDRX (0x1u << 27)
342 #define ADC_ISR_RXBUFF (0x1u << 28)
343 /* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */
344 #define ADC_OVER_OVRE0 (0x1u << 0)
345 #define ADC_OVER_OVRE1 (0x1u << 1)
346 #define ADC_OVER_OVRE2 (0x1u << 2)
347 #define ADC_OVER_OVRE3 (0x1u << 3)
348 #define ADC_OVER_OVRE4 (0x1u << 4)
349 #define ADC_OVER_OVRE5 (0x1u << 5)
350 #define ADC_OVER_OVRE6 (0x1u << 6)
351 #define ADC_OVER_OVRE7 (0x1u << 7)
352 #define ADC_OVER_OVRE8 (0x1u << 8)
353 #define ADC_OVER_OVRE9 (0x1u << 9)
354 #define ADC_OVER_OVRE10 (0x1u << 10)
355 #define ADC_OVER_OVRE11 (0x1u << 11)
356 #define ADC_OVER_OVRE12 (0x1u << 12)
357 #define ADC_OVER_OVRE13 (0x1u << 13)
358 #define ADC_OVER_OVRE14 (0x1u << 14)
359 #define ADC_OVER_OVRE15 (0x1u << 15)
360 /* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */
361 #define ADC_EMR_CMPMODE_Pos 0
362 #define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos)
363 #define ADC_EMR_CMPMODE_LOW (0x0u << 0)
364 #define ADC_EMR_CMPMODE_HIGH (0x1u << 0)
365 #define ADC_EMR_CMPMODE_IN (0x2u << 0)
366 #define ADC_EMR_CMPMODE_OUT (0x3u << 0)
367 #define ADC_EMR_CMPSEL_Pos 4
368 #define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos)
369 #define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))
370 #define ADC_EMR_CMPALL (0x1u << 9)
371 #define ADC_EMR_CMPFILTER_Pos 12
372 #define ADC_EMR_CMPFILTER_Msk (0x3u << ADC_EMR_CMPFILTER_Pos)
373 #define ADC_EMR_CMPFILTER(value) ((ADC_EMR_CMPFILTER_Msk & ((value) << ADC_EMR_CMPFILTER_Pos)))
374 #define ADC_EMR_TAG (0x1u << 24)
375 /* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */
376 #define ADC_CWR_LOWTHRES_Pos 0
377 #define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos)
378 #define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))
379 #define ADC_CWR_HIGHTHRES_Pos 16
380 #define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos)
381 #define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))
382 /* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */
383 #define ADC_CGR_GAIN0_Pos 0
384 #define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos)
385 #define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos)))
386 #define ADC_CGR_GAIN1_Pos 2
387 #define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos)
388 #define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos)))
389 #define ADC_CGR_GAIN2_Pos 4
390 #define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos)
391 #define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos)))
392 #define ADC_CGR_GAIN3_Pos 6
393 #define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos)
394 #define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos)))
395 #define ADC_CGR_GAIN4_Pos 8
396 #define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos)
397 #define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos)))
398 #define ADC_CGR_GAIN5_Pos 10
399 #define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos)
400 #define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos)))
401 #define ADC_CGR_GAIN6_Pos 12
402 #define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos)
403 #define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos)))
404 #define ADC_CGR_GAIN7_Pos 14
405 #define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos)
406 #define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos)))
407 #define ADC_CGR_GAIN8_Pos 16
408 #define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos)
409 #define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos)))
410 #define ADC_CGR_GAIN9_Pos 18
411 #define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos)
412 #define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos)))
413 #define ADC_CGR_GAIN10_Pos 20
414 #define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos)
415 #define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos)))
416 #define ADC_CGR_GAIN11_Pos 22
417 #define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos)
418 #define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos)))
419 #define ADC_CGR_GAIN12_Pos 24
420 #define ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos)
421 #define ADC_CGR_GAIN12(value) ((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos)))
422 #define ADC_CGR_GAIN13_Pos 26
423 #define ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos)
424 #define ADC_CGR_GAIN13(value) ((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos)))
425 #define ADC_CGR_GAIN14_Pos 28
426 #define ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos)
427 #define ADC_CGR_GAIN14(value) ((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos)))
428 #define ADC_CGR_GAIN15_Pos 30
429 #define ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos)
430 #define ADC_CGR_GAIN15(value) ((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos)))
431 /* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */
432 #define ADC_COR_OFF0 (0x1u << 0)
433 #define ADC_COR_OFF1 (0x1u << 1)
434 #define ADC_COR_OFF2 (0x1u << 2)
435 #define ADC_COR_OFF3 (0x1u << 3)
436 #define ADC_COR_OFF4 (0x1u << 4)
437 #define ADC_COR_OFF5 (0x1u << 5)
438 #define ADC_COR_OFF6 (0x1u << 6)
439 #define ADC_COR_OFF7 (0x1u << 7)
440 #define ADC_COR_OFF8 (0x1u << 8)
441 #define ADC_COR_OFF9 (0x1u << 9)
442 #define ADC_COR_OFF10 (0x1u << 10)
443 #define ADC_COR_OFF11 (0x1u << 11)
444 #define ADC_COR_OFF12 (0x1u << 12)
445 #define ADC_COR_OFF13 (0x1u << 13)
446 #define ADC_COR_OFF14 (0x1u << 14)
447 #define ADC_COR_OFF15 (0x1u << 15)
448 #define ADC_COR_DIFF0 (0x1u << 16)
449 #define ADC_COR_DIFF1 (0x1u << 17)
450 #define ADC_COR_DIFF2 (0x1u << 18)
451 #define ADC_COR_DIFF3 (0x1u << 19)
452 #define ADC_COR_DIFF4 (0x1u << 20)
453 #define ADC_COR_DIFF5 (0x1u << 21)
454 #define ADC_COR_DIFF6 (0x1u << 22)
455 #define ADC_COR_DIFF7 (0x1u << 23)
456 #define ADC_COR_DIFF8 (0x1u << 24)
457 #define ADC_COR_DIFF9 (0x1u << 25)
458 #define ADC_COR_DIFF10 (0x1u << 26)
459 #define ADC_COR_DIFF11 (0x1u << 27)
460 #define ADC_COR_DIFF12 (0x1u << 28)
461 #define ADC_COR_DIFF13 (0x1u << 29)
462 #define ADC_COR_DIFF14 (0x1u << 30)
463 #define ADC_COR_DIFF15 (0x1u << 31)
464 /* -------- ADC_CDR[15] : (ADC Offset: 0x50) Channel Data Register -------- */
465 #define ADC_CDR_DATA_Pos 0
466 #define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos)
467 /* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */
468 #define ADC_ACR_TSON (0x1u << 4)
469 #define ADC_ACR_IBCTL_Pos 8
470 #define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos)
471 #define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos)))
472 /* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */
473 #define ADC_WPMR_WPEN (0x1u << 0)
474 #define ADC_WPMR_WPKEY_Pos 8
475 #define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos)
476 #define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))
477 /* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */
478 #define ADC_WPSR_WPVS (0x1u << 0)
479 #define ADC_WPSR_WPVSRC_Pos 8
480 #define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos)
481 /* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
482 #define ADC_RPR_RXPTR_Pos 0
483 #define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos)
484 #define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))
485 /* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
486 #define ADC_RCR_RXCTR_Pos 0
487 #define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos)
488 #define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))
489 /* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
490 #define ADC_RNPR_RXNPTR_Pos 0
491 #define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos)
492 #define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))
493 /* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
494 #define ADC_RNCR_RXNCTR_Pos 0
495 #define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos)
496 #define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))
497 /* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
498 #define ADC_PTCR_RXTEN (0x1u << 0)
499 #define ADC_PTCR_RXTDIS (0x1u << 1)
500 #define ADC_PTCR_TXTEN (0x1u << 8)
501 #define ADC_PTCR_TXTDIS (0x1u << 9)
502 /* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
503 #define ADC_PTSR_RXTEN (0x1u << 0)
504 #define ADC_PTSR_TXTEN (0x1u << 8)
507 
508 
509 #endif /* _SAM3S8_ADC_COMPONENT_ */
RwReg
volatile uint32_t RwReg
Definition: sam3n00a.h:54
WoReg
volatile uint32_t WoReg
Definition: sam3n00a.h:53
RoReg
volatile const uint32_t RoReg
Definition: sam3n00a.h:49
Adc
Adc hardware registers.
Definition: component_adc.h:41