Robobo
component_dacc.h
1 /* ----------------------------------------------------------------------------
2  * SAM Software Package License
3  * ----------------------------------------------------------------------------
4  * Copyright (c) 2012, Atmel Corporation
5  *
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following condition is met:
10  *
11  * - Redistributions of source code must retain the above copyright notice,
12  * this list of conditions and the disclaimer below.
13  *
14  * Atmel's name may not be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
20  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
23  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  * ----------------------------------------------------------------------------
28  */
29 
30 #ifndef _SAM3XA_DACC_COMPONENT_
31 #define _SAM3XA_DACC_COMPONENT_
32 
33 /* ============================================================================= */
35 /* ============================================================================= */
38 
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40 
41 typedef struct {
42  WoReg DACC_CR;
43  RwReg DACC_MR;
44  RoReg Reserved1[2];
45  WoReg DACC_CHER;
46  WoReg DACC_CHDR;
47  RoReg DACC_CHSR;
48  RoReg Reserved2[1];
49  WoReg DACC_CDR;
50  WoReg DACC_IER;
51  WoReg DACC_IDR;
52  RoReg DACC_IMR;
53  RoReg DACC_ISR;
54  RoReg Reserved3[24];
55  RwReg DACC_ACR;
56  RoReg Reserved4[19];
57  RwReg DACC_WPMR;
58  RoReg DACC_WPSR;
59  RoReg Reserved5[7];
60  RwReg DACC_TPR;
61  RwReg DACC_TCR;
62  RoReg Reserved6[2];
63  RwReg DACC_TNPR;
64  RwReg DACC_TNCR;
65  WoReg DACC_PTCR;
66  RoReg DACC_PTSR;
67 } Dacc;
68 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
69 /* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
70 #define DACC_CR_SWRST (0x1u << 0)
71 /* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
72 #define DACC_MR_TRGEN (0x1u << 0)
73 #define DACC_MR_TRGEN_DIS (0x0u << 0)
74 #define DACC_MR_TRGEN_EN (0x1u << 0)
75 #define DACC_MR_TRGSEL_Pos 1
76 #define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos)
77 #define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos)))
78 #define DACC_MR_WORD (0x1u << 4)
79 #define DACC_MR_WORD_HALF (0x0u << 4)
80 #define DACC_MR_WORD_WORD (0x1u << 4)
81 #define DACC_MR_SLEEP (0x1u << 5)
82 #define DACC_MR_FASTWKUP (0x1u << 6)
83 #define DACC_MR_REFRESH_Pos 8
84 #define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos)
85 #define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))
86 #define DACC_MR_USER_SEL_Pos 16
87 #define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos)
88 #define DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16)
89 #define DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16)
90 #define DACC_MR_TAG (0x1u << 20)
91 #define DACC_MR_TAG_DIS (0x0u << 20)
92 #define DACC_MR_TAG_EN (0x1u << 20)
93 #define DACC_MR_MAXS (0x1u << 21)
94 #define DACC_MR_MAXS_NORMAL (0x0u << 21)
95 #define DACC_MR_MAXS_MAXIMUM (0x1u << 21)
96 #define DACC_MR_STARTUP_Pos 24
97 #define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos)
98 #define DACC_MR_STARTUP_0 (0x0u << 24)
99 #define DACC_MR_STARTUP_8 (0x1u << 24)
100 #define DACC_MR_STARTUP_16 (0x2u << 24)
101 #define DACC_MR_STARTUP_24 (0x3u << 24)
102 #define DACC_MR_STARTUP_64 (0x4u << 24)
103 #define DACC_MR_STARTUP_80 (0x5u << 24)
104 #define DACC_MR_STARTUP_96 (0x6u << 24)
105 #define DACC_MR_STARTUP_112 (0x7u << 24)
106 #define DACC_MR_STARTUP_512 (0x8u << 24)
107 #define DACC_MR_STARTUP_576 (0x9u << 24)
108 #define DACC_MR_STARTUP_640 (0xAu << 24)
109 #define DACC_MR_STARTUP_704 (0xBu << 24)
110 #define DACC_MR_STARTUP_768 (0xCu << 24)
111 #define DACC_MR_STARTUP_832 (0xDu << 24)
112 #define DACC_MR_STARTUP_896 (0xEu << 24)
113 #define DACC_MR_STARTUP_960 (0xFu << 24)
114 #define DACC_MR_STARTUP_1024 (0x10u << 24)
115 #define DACC_MR_STARTUP_1088 (0x11u << 24)
116 #define DACC_MR_STARTUP_1152 (0x12u << 24)
117 #define DACC_MR_STARTUP_1216 (0x13u << 24)
118 #define DACC_MR_STARTUP_1280 (0x14u << 24)
119 #define DACC_MR_STARTUP_1344 (0x15u << 24)
120 #define DACC_MR_STARTUP_1408 (0x16u << 24)
121 #define DACC_MR_STARTUP_1472 (0x17u << 24)
122 #define DACC_MR_STARTUP_1536 (0x18u << 24)
123 #define DACC_MR_STARTUP_1600 (0x19u << 24)
124 #define DACC_MR_STARTUP_1664 (0x1Au << 24)
125 #define DACC_MR_STARTUP_1728 (0x1Bu << 24)
126 #define DACC_MR_STARTUP_1792 (0x1Cu << 24)
127 #define DACC_MR_STARTUP_1856 (0x1Du << 24)
128 #define DACC_MR_STARTUP_1920 (0x1Eu << 24)
129 #define DACC_MR_STARTUP_1984 (0x1Fu << 24)
130 /* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */
131 #define DACC_CHER_CH0 (0x1u << 0)
132 #define DACC_CHER_CH1 (0x1u << 1)
133 /* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */
134 #define DACC_CHDR_CH0 (0x1u << 0)
135 #define DACC_CHDR_CH1 (0x1u << 1)
136 /* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */
137 #define DACC_CHSR_CH0 (0x1u << 0)
138 #define DACC_CHSR_CH1 (0x1u << 1)
139 /* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */
140 #define DACC_CDR_DATA_Pos 0
141 #define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos)
142 #define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))
143 /* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */
144 #define DACC_IER_TXRDY (0x1u << 0)
145 #define DACC_IER_EOC (0x1u << 1)
146 #define DACC_IER_ENDTX (0x1u << 2)
147 #define DACC_IER_TXBUFE (0x1u << 3)
148 /* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */
149 #define DACC_IDR_TXRDY (0x1u << 0)
150 #define DACC_IDR_EOC (0x1u << 1)
151 #define DACC_IDR_ENDTX (0x1u << 2)
152 #define DACC_IDR_TXBUFE (0x1u << 3)
153 /* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */
154 #define DACC_IMR_TXRDY (0x1u << 0)
155 #define DACC_IMR_EOC (0x1u << 1)
156 #define DACC_IMR_ENDTX (0x1u << 2)
157 #define DACC_IMR_TXBUFE (0x1u << 3)
158 /* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */
159 #define DACC_ISR_TXRDY (0x1u << 0)
160 #define DACC_ISR_EOC (0x1u << 1)
161 #define DACC_ISR_ENDTX (0x1u << 2)
162 #define DACC_ISR_TXBUFE (0x1u << 3)
163 /* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */
164 #define DACC_ACR_IBCTLCH0_Pos 0
165 #define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos)
166 #define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))
167 #define DACC_ACR_IBCTLCH1_Pos 2
168 #define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos)
169 #define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))
170 #define DACC_ACR_IBCTLDACCORE_Pos 8
171 #define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos)
172 #define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos)))
173 /* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */
174 #define DACC_WPMR_WPEN (0x1u << 0)
175 #define DACC_WPMR_WPKEY_Pos 8
176 #define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos)
177 #define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
178 /* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */
179 #define DACC_WPSR_WPROTERR (0x1u << 0)
180 #define DACC_WPSR_WPROTADDR_Pos 8
181 #define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos)
182 /* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */
183 #define DACC_TPR_TXPTR_Pos 0
184 #define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos)
185 #define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos)))
186 /* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */
187 #define DACC_TCR_TXCTR_Pos 0
188 #define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos)
189 #define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos)))
190 /* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */
191 #define DACC_TNPR_TXNPTR_Pos 0
192 #define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos)
193 #define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos)))
194 /* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */
195 #define DACC_TNCR_TXNCTR_Pos 0
196 #define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos)
197 #define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos)))
198 /* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */
199 #define DACC_PTCR_RXTEN (0x1u << 0)
200 #define DACC_PTCR_RXTDIS (0x1u << 1)
201 #define DACC_PTCR_TXTEN (0x1u << 8)
202 #define DACC_PTCR_TXTDIS (0x1u << 9)
203 /* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */
204 #define DACC_PTSR_RXTEN (0x1u << 0)
205 #define DACC_PTSR_TXTEN (0x1u << 8)
208 
209 
210 #endif /* _SAM3XA_DACC_COMPONENT_ */
RwReg
volatile uint32_t RwReg
Definition: sam3n00a.h:54
WoReg
volatile uint32_t WoReg
Definition: sam3n00a.h:53
Dacc
Dacc hardware registers.
Definition: component_dacc.h:41
RoReg
volatile const uint32_t RoReg
Definition: sam3n00a.h:49