Dacc hardware registers. More...

Public Attributes
WoReg	DACC_CR
	(Dacc Offset: 0x00) Control Register

RwReg	DACC_MR
	(Dacc Offset: 0x04) Mode Register

WoReg	DACC_CDR
	(Dacc Offset: 0x08) Conversion Data Register More...

WoReg	DACC_IER
	(Dacc Offset: 0x0C) Interrupt Enable Register More...

WoReg	DACC_IDR
	(Dacc Offset: 0x10) Interrupt Disable Register More...

RoReg	DACC_IMR
	(Dacc Offset: 0x14) Interrupt Mask Register More...

RoReg	DACC_ISR
	(Dacc Offset: 0x18) Interrupt Status Register More...

RoReg	Reserved1 [50]

RwReg	DACC_WPMR
	(Dacc Offset: 0xE4) Write Protect Mode Register More...

RoReg	DACC_WPSR
	(Dacc Offset: 0xE8) Write Protect Status Register More...

RoReg	Reserved2 [7]

RwReg	DACC_TPR
	(Dacc Offset: 0x108) Transmit Pointer Register

RwReg	DACC_TCR
	(Dacc Offset: 0x10C) Transmit Counter Register

RoReg	Reserved3 [2]

RwReg	DACC_TNPR
	(Dacc Offset: 0x118) Transmit Next Pointer Register

RwReg	DACC_TNCR
	(Dacc Offset: 0x11C) Transmit Next Counter Register

WoReg	DACC_PTCR
	(Dacc Offset: 0x120) Transfer Control Register

RoReg	DACC_PTSR
	(Dacc Offset: 0x124) Transfer Status Register

WoReg	DACC_CHER
	(Dacc Offset: 0x10) Channel Enable Register

WoReg	DACC_CHDR
	(Dacc Offset: 0x14) Channel Disable Register

RoReg	DACC_CHSR
	(Dacc Offset: 0x18) Channel Status Register

RwReg	DACC_ACR
	(Dacc Offset: 0x94) Analog Current Register

RoReg	Reserved4 [19]

RoReg	Reserved5 [7]

RoReg	Reserved6 [2]

Detailed Description

Dacc hardware registers.

Member Data Documentation

WoReg Dacc::DACC_CDR

(Dacc Offset: 0x08) Conversion Data Register

(Dacc Offset: 0x20) Conversion Data Register

WoReg Dacc::DACC_IDR

(Dacc Offset: 0x10) Interrupt Disable Register

(Dacc Offset: 0x28) Interrupt Disable Register

WoReg Dacc::DACC_IER

(Dacc Offset: 0x0C) Interrupt Enable Register

(Dacc Offset: 0x24) Interrupt Enable Register

RoReg Dacc::DACC_IMR

(Dacc Offset: 0x14) Interrupt Mask Register

(Dacc Offset: 0x2C) Interrupt Mask Register

RoReg Dacc::DACC_ISR

(Dacc Offset: 0x18) Interrupt Status Register

(Dacc Offset: 0x30) Interrupt Status Register

RwReg Dacc::DACC_WPMR

(Dacc Offset: 0xE4) Write Protect Mode Register

(Dacc Offset: 0xE4) Write Protect Mode register

RoReg Dacc::DACC_WPSR

(Dacc Offset: 0xE8) Write Protect Status Register

(Dacc Offset: 0xE8) Write Protect Status register

The documentation for this struct was generated from the following file: