Classes
struct	Dacc
	Dacc hardware registers. More...

Macros
#define	DACC_CR_SWRST (0x1u << 0)
	(DACC_CR) Software Reset

#define	DACC_MR_TRGEN (0x1u << 0)
	(DACC_MR) Trigger Enable

#define	DACC_MR_TRGEN_DIS (0x0u << 0)
	(DACC_MR) External trigger mode disabled. DACC in free running mode.

#define	DACC_MR_TRGEN_EN (0x1u << 0)
	(DACC_MR) External trigger mode enabled.

#define	DACC_MR_TRGSEL_Pos 1

#define	DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos)
	(DACC_MR) Trigger Selection

#define	DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos)))

#define	DACC_MR_WORD (0x1u << 4)
	(DACC_MR) Word Transfer

#define	DACC_MR_WORD_HALF (0x0u << 4)
	(DACC_MR) Half-Word transfer

#define	DACC_MR_WORD_WORD (0x1u << 4)
	(DACC_MR) Word Transfer

#define	DACC_MR_SLEEP (0x1u << 5)
	(DACC_MR) Sleep Mode

#define	DACC_MR_FASTWKUP (0x1u << 6)
	(DACC_MR) Fast Wake up Mode

#define	DACC_MR_REFRESH_Pos 8

#define	DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos)
	(DACC_MR) Refresh Period

#define	DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))

#define	DACC_MR_USER_SEL_Pos 16

#define	DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos)
	(DACC_MR) User Channel Selection

#define	DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16)
	(DACC_MR) Channel 0

#define	DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16)
	(DACC_MR) Channel 1

#define	DACC_MR_TAG (0x1u << 20)
	(DACC_MR) Tag Selection Mode

#define	DACC_MR_TAG_DIS (0x0u << 20)
	(DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion.

#define	DACC_MR_TAG_EN (0x1u << 20)
	(DACC_MR) Tag selection mode enabled

#define	DACC_MR_MAXS (0x1u << 21)
	(DACC_MR) Max Speed Mode

#define	DACC_MR_STARTUP_Pos 24

#define	DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos)
	(DACC_MR) Startup Time Selection

#define	DACC_MR_STARTUP_0 (0x0u << 24)
	(DACC_MR) 0 periods of DACClock

#define	DACC_MR_STARTUP_8 (0x1u << 24)
	(DACC_MR) 8 periods of DACClock

#define	DACC_MR_STARTUP_16 (0x2u << 24)
	(DACC_MR) 16 periods of DACClock

#define	DACC_MR_STARTUP_24 (0x3u << 24)
	(DACC_MR) 24 periods of DACClock

#define	DACC_MR_STARTUP_64 (0x4u << 24)
	(DACC_MR) 64 periods of DACClock

#define	DACC_MR_STARTUP_80 (0x5u << 24)
	(DACC_MR) 80 periods of DACClock

#define	DACC_MR_STARTUP_96 (0x6u << 24)
	(DACC_MR) 96 periods of DACClock

#define	DACC_MR_STARTUP_112 (0x7u << 24)
	(DACC_MR) 112 periods of DACClock

#define	DACC_MR_STARTUP_512 (0x8u << 24)
	(DACC_MR) 512 periods of DACClock

#define	DACC_MR_STARTUP_576 (0x9u << 24)
	(DACC_MR) 576 periods of DACClock

#define	DACC_MR_STARTUP_640 (0xAu << 24)
	(DACC_MR) 640 periods of DACClock

#define	DACC_MR_STARTUP_704 (0xBu << 24)
	(DACC_MR) 704 periods of DACClock

#define	DACC_MR_STARTUP_768 (0xCu << 24)
	(DACC_MR) 768 periods of DACClock

#define	DACC_MR_STARTUP_832 (0xDu << 24)
	(DACC_MR) 832 periods of DACClock

#define	DACC_MR_STARTUP_896 (0xEu << 24)
	(DACC_MR) 896 periods of DACClock

#define	DACC_MR_STARTUP_960 (0xFu << 24)
	(DACC_MR) 960 periods of DACClock

#define	DACC_MR_STARTUP_1024 (0x10u << 24)
	(DACC_MR) 1024 periods of DACClock

#define	DACC_MR_STARTUP_1088 (0x11u << 24)
	(DACC_MR) 1088 periods of DACClock

#define	DACC_MR_STARTUP_1152 (0x12u << 24)
	(DACC_MR) 1152 periods of DACClock

#define	DACC_MR_STARTUP_1216 (0x13u << 24)
	(DACC_MR) 1216 periods of DACClock

#define	DACC_MR_STARTUP_1280 (0x14u << 24)
	(DACC_MR) 1280 periods of DACClock

#define	DACC_MR_STARTUP_1344 (0x15u << 24)
	(DACC_MR) 1344 periods of DACClock

#define	DACC_MR_STARTUP_1408 (0x16u << 24)
	(DACC_MR) 1408 periods of DACClock

#define	DACC_MR_STARTUP_1472 (0x17u << 24)
	(DACC_MR) 1472 periods of DACClock

#define	DACC_MR_STARTUP_1536 (0x18u << 24)
	(DACC_MR) 1536 periods of DACClock

#define	DACC_MR_STARTUP_1600 (0x19u << 24)
	(DACC_MR) 1600 periods of DACClock

#define	DACC_MR_STARTUP_1664 (0x1Au << 24)
	(DACC_MR) 1664 periods of DACClock

#define	DACC_MR_STARTUP_1728 (0x1Bu << 24)
	(DACC_MR) 1728 periods of DACClock

#define	DACC_MR_STARTUP_1792 (0x1Cu << 24)
	(DACC_MR) 1792 periods of DACClock

#define	DACC_MR_STARTUP_1856 (0x1Du << 24)
	(DACC_MR) 1856 periods of DACClock

#define	DACC_MR_STARTUP_1920 (0x1Eu << 24)
	(DACC_MR) 1920 periods of DACClock

#define	DACC_MR_STARTUP_1984 (0x1Fu << 24)
	(DACC_MR) 1984 periods of DACClock

#define	DACC_CHER_CH0 (0x1u << 0)
	(DACC_CHER) Channel 0 Enable

#define	DACC_CHER_CH1 (0x1u << 1)
	(DACC_CHER) Channel 1 Enable

#define	DACC_CHDR_CH0 (0x1u << 0)
	(DACC_CHDR) Channel 0 Disable

#define	DACC_CHDR_CH1 (0x1u << 1)
	(DACC_CHDR) Channel 1 Disable

#define	DACC_CHSR_CH0 (0x1u << 0)
	(DACC_CHSR) Channel 0 Status

#define	DACC_CHSR_CH1 (0x1u << 1)
	(DACC_CHSR) Channel 1 Status

#define	DACC_CDR_DATA_Pos 0

#define	DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos)
	(DACC_CDR) Data to Convert

#define	DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))

#define	DACC_IER_TXRDY (0x1u << 0)
	(DACC_IER) Transmit Ready Interrupt Enable

#define	DACC_IER_EOC (0x1u << 1)
	(DACC_IER) End of Conversion Interrupt Enable

#define	DACC_IER_ENDTX (0x1u << 2)
	(DACC_IER) End of Transmit Buffer Interrupt Enable

#define	DACC_IER_TXBUFE (0x1u << 3)
	(DACC_IER) Transmit Buffer Empty Interrupt Enable

#define	DACC_IDR_TXRDY (0x1u << 0)
	(DACC_IDR) Transmit Ready Interrupt Disable.

#define	DACC_IDR_EOC (0x1u << 1)
	(DACC_IDR) End of Conversion Interrupt Disable

#define	DACC_IDR_ENDTX (0x1u << 2)
	(DACC_IDR) End of Transmit Buffer Interrupt Disable

#define	DACC_IDR_TXBUFE (0x1u << 3)
	(DACC_IDR) Transmit Buffer Empty Interrupt Disable

#define	DACC_IMR_TXRDY (0x1u << 0)
	(DACC_IMR) Transmit Ready Interrupt Mask

#define	DACC_IMR_EOC (0x1u << 1)
	(DACC_IMR) End of Conversion Interrupt Mask

#define	DACC_IMR_ENDTX (0x1u << 2)
	(DACC_IMR) End of Transmit Buffer Interrupt Mask

#define	DACC_IMR_TXBUFE (0x1u << 3)
	(DACC_IMR) Transmit Buffer Empty Interrupt Mask

#define	DACC_ISR_TXRDY (0x1u << 0)
	(DACC_ISR) Transmit Ready Interrupt Flag

#define	DACC_ISR_EOC (0x1u << 1)
	(DACC_ISR) End of Conversion Interrupt Flag

#define	DACC_ISR_ENDTX (0x1u << 2)
	(DACC_ISR) End of DMA Interrupt Flag

#define	DACC_ISR_TXBUFE (0x1u << 3)
	(DACC_ISR) Transmit Buffer Empty

#define	DACC_ACR_IBCTLCH0_Pos 0

#define	DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos)
	(DACC_ACR) Analog Output Current Control

#define	DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))

#define	DACC_ACR_IBCTLCH1_Pos 2

#define	DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos)
	(DACC_ACR) Analog Output Current Control

#define	DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))

#define	DACC_ACR_IBCTLDACCORE_Pos 8

#define	DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos)
	(DACC_ACR) Bias Current Control for DAC Core

#define	DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos)))

#define	DACC_WPMR_WPEN (0x1u << 0)
	(DACC_WPMR) Write Protect Enable

#define	DACC_WPMR_WPKEY_Pos 8

#define	DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos)
	(DACC_WPMR) Write Protect KEY

#define	DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))

#define	DACC_WPSR_WPROTERR (0x1u << 0)
	(DACC_WPSR) Write protection error

#define	DACC_WPSR_WPROTADDR_Pos 8

#define	DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos)
	(DACC_WPSR) Write protection error address

#define	DACC_TPR_TXPTR_Pos 0

#define	DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos)
	(DACC_TPR) Transmit Counter Register

#define	DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos)))

#define	DACC_TCR_TXCTR_Pos 0

#define	DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos)
	(DACC_TCR) Transmit Counter Register

#define	DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos)))

#define	DACC_TNPR_TXNPTR_Pos 0

#define	DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos)
	(DACC_TNPR) Transmit Next Pointer

#define	DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos)))

#define	DACC_TNCR_TXNCTR_Pos 0

#define	DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos)
	(DACC_TNCR) Transmit Counter Next

#define	DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos)))

#define	DACC_PTCR_RXTEN (0x1u << 0)
	(DACC_PTCR) Receiver Transfer Enable

#define	DACC_PTCR_RXTDIS (0x1u << 1)
	(DACC_PTCR) Receiver Transfer Disable

#define	DACC_PTCR_TXTEN (0x1u << 8)
	(DACC_PTCR) Transmitter Transfer Enable

#define	DACC_PTCR_TXTDIS (0x1u << 9)
	(DACC_PTCR) Transmitter Transfer Disable

#define	DACC_PTSR_RXTEN (0x1u << 0)
	(DACC_PTSR) Receiver Transfer Enable

#define	DACC_PTSR_TXTEN (0x1u << 8)
	(DACC_PTSR) Transmitter Transfer Enable

Detailed Description

SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller

Classes

Macros

Detailed Description