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#define | DACC_CR_SWRST (0x1u << 0) |
| | (DACC_CR) Software Reset
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#define | DACC_MR_TRGEN (0x1u << 0) |
| | (DACC_MR) Trigger Enable
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#define | DACC_MR_TRGSEL_Pos 1 |
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#define | DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) |
| | (DACC_MR) Trigger Selection
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#define | DACC_MR_TRGSEL_TRGSEL0 (0x0u << 1) |
| | (DACC_MR) External trigger
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#define | DACC_MR_TRGSEL_TRGSEL1 (0x1u << 1) |
| | (DACC_MR) TIO Output of the Timer Counter Channel 0
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#define | DACC_MR_TRGSEL_TRGSEL2 (0x2u << 1) |
| | (DACC_MR) TIO Output of the Timer Counter Channel 1
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#define | DACC_MR_TRGSEL_TRGSEL3 (0x3u << 1) |
| | (DACC_MR) TIO Output of the Timer Counter Channel 2
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#define | DACC_MR_DACEN (0x1u << 4) |
| | (DACC_MR) DAC enable
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#define | DACC_MR_WORD (0x1u << 5) |
| | (DACC_MR) Word Transfer
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#define | DACC_MR_STARTUP_Pos 8 |
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#define | DACC_MR_STARTUP_Msk (0xffu << DACC_MR_STARTUP_Pos) |
| | (DACC_MR) Startup Time Selection
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#define | DACC_MR_STARTUP(value) ((DACC_MR_STARTUP_Msk & ((value) << DACC_MR_STARTUP_Pos))) |
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#define | DACC_MR_CLKDIV_Pos 16 |
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#define | DACC_MR_CLKDIV_Msk (0xffffu << DACC_MR_CLKDIV_Pos) |
| | (DACC_MR) DAC Clock Divider for Internal Trigger
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#define | DACC_MR_CLKDIV(value) ((DACC_MR_CLKDIV_Msk & ((value) << DACC_MR_CLKDIV_Pos))) |
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#define | DACC_CDR_DATA_Pos 0 |
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#define | DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) |
| | (DACC_CDR) Data to Convert
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#define | DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos))) |
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#define | DACC_IER_TXRDY (0x1u << 0) |
| | (DACC_IER) Transmission Ready Interrupt Enable
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#define | DACC_IER_ENDTX (0x1u << 1) |
| | (DACC_IER) End of PDC Interrupt Enable
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#define | DACC_IER_TXBUFE (0x1u << 2) |
| | (DACC_IER) Buffer Empty Interrupt Enable
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#define | DACC_IDR_TXRDY (0x1u << 0) |
| | (DACC_IDR) Transmission Ready Interrupt Disable
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#define | DACC_IDR_ENDTX (0x1u << 1) |
| | (DACC_IDR) End of PDC Interrupt Disable
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#define | DACC_IDR_TXBUFE (0x1u << 2) |
| | (DACC_IDR) Buffer Empty Interrupt Disable
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#define | DACC_IMR_TXRDY (0x1u << 0) |
| | (DACC_IMR) Transmission Ready Interrupt Mask
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#define | DACC_IMR_ENDTX (0x1u << 1) |
| | (DACC_IMR) End of PDC Interrupt Mask
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#define | DACC_IMR_TXBUFE (0x1u << 2) |
| | (DACC_IMR) Buffer Empty Interrupt Mask
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#define | DACC_ISR_TXRDY (0x1u << 0) |
| | (DACC_ISR) Transmission Ready Interrupt Flag
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#define | DACC_ISR_ENDTX (0x1u << 1) |
| | (DACC_ISR) End of PDC Interrupt Flag
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#define | DACC_ISR_TXBUFE (0x1u << 2) |
| | (DACC_ISR) Buffer Empty Interrupt Flag
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#define | DACC_WPMR_WPEN (0x1u << 0) |
| | (DACC_WPMR) Write Protect Enable
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#define | DACC_WPMR_WPKEY_Pos 8 |
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#define | DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) |
| | (DACC_WPMR) Write Protect KEY
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#define | DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))) |
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#define | DACC_WPSR_WPROTERR (0x1u << 0) |
| | (DACC_WPSR) Write protection error
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#define | DACC_WPSR_WPROTADDR_Pos 8 |
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#define | DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) |
| | (DACC_WPSR) Write protection error address
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#define | DACC_TPR_TXPTR_Pos 0 |
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#define | DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) |
| | (DACC_TPR) Transmit Counter Register
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#define | DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos))) |
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#define | DACC_TCR_TXCTR_Pos 0 |
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#define | DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) |
| | (DACC_TCR) Transmit Counter Register
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#define | DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos))) |
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#define | DACC_TNPR_TXNPTR_Pos 0 |
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#define | DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) |
| | (DACC_TNPR) Transmit Next Pointer
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#define | DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos))) |
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#define | DACC_TNCR_TXNCTR_Pos 0 |
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#define | DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) |
| | (DACC_TNCR) Transmit Counter Next
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#define | DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos))) |
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#define | DACC_PTCR_RXTEN (0x1u << 0) |
| | (DACC_PTCR) Receiver Transfer Enable
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#define | DACC_PTCR_RXTDIS (0x1u << 1) |
| | (DACC_PTCR) Receiver Transfer Disable
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#define | DACC_PTCR_TXTEN (0x1u << 8) |
| | (DACC_PTCR) Transmitter Transfer Enable
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#define | DACC_PTCR_TXTDIS (0x1u << 9) |
| | (DACC_PTCR) Transmitter Transfer Disable
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#define | DACC_PTSR_RXTEN (0x1u << 0) |
| | (DACC_PTSR) Receiver Transfer Enable
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#define | DACC_PTSR_TXTEN (0x1u << 8) |
| | (DACC_PTSR) Transmitter Transfer Enable
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1.8.11 
