Robobo
component_spi.h
1 /* ----------------------------------------------------------------------------
2  * SAM Software Package License
3  * ----------------------------------------------------------------------------
4  * Copyright (c) 2012, Atmel Corporation
5  *
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following condition is met:
10  *
11  * - Redistributions of source code must retain the above copyright notice,
12  * this list of conditions and the disclaimer below.
13  *
14  * Atmel's name may not be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
20  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
23  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  * ----------------------------------------------------------------------------
28  */
29 
30 #ifndef _SAM3S8_SPI_COMPONENT_
31 #define _SAM3S8_SPI_COMPONENT_
32 
33 /* ============================================================================= */
35 /* ============================================================================= */
38 
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40 
41 typedef struct {
42  WoReg SPI_CR;
43  RwReg SPI_MR;
44  RoReg SPI_RDR;
45  WoReg SPI_TDR;
46  RoReg SPI_SR;
47  WoReg SPI_IER;
48  WoReg SPI_IDR;
49  RoReg SPI_IMR;
50  RoReg Reserved1[4];
51  RwReg SPI_CSR[4];
52  RoReg Reserved2[41];
53  RwReg SPI_WPMR;
54  RoReg SPI_WPSR;
55  RoReg Reserved3[5];
56  RwReg SPI_RPR;
57  RwReg SPI_RCR;
58  RwReg SPI_TPR;
59  RwReg SPI_TCR;
60  RwReg SPI_RNPR;
61  RwReg SPI_RNCR;
62  RwReg SPI_TNPR;
63  RwReg SPI_TNCR;
64  WoReg SPI_PTCR;
65  RoReg SPI_PTSR;
66 } Spi;
67 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
68 /* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
69 #define SPI_CR_SPIEN (0x1u << 0)
70 #define SPI_CR_SPIDIS (0x1u << 1)
71 #define SPI_CR_SWRST (0x1u << 7)
72 #define SPI_CR_LASTXFER (0x1u << 24)
73 /* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
74 #define SPI_MR_MSTR (0x1u << 0)
75 #define SPI_MR_PS (0x1u << 1)
76 #define SPI_MR_PCSDEC (0x1u << 2)
77 #define SPI_MR_MODFDIS (0x1u << 4)
78 #define SPI_MR_WDRBT (0x1u << 5)
79 #define SPI_MR_LLB (0x1u << 7)
80 #define SPI_MR_PCS_Pos 16
81 #define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos)
82 #define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
83 #define SPI_MR_DLYBCS_Pos 24
84 #define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos)
85 #define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
86 /* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
87 #define SPI_RDR_RD_Pos 0
88 #define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos)
89 #define SPI_RDR_PCS_Pos 16
90 #define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos)
91 /* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
92 #define SPI_TDR_TD_Pos 0
93 #define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos)
94 #define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
95 #define SPI_TDR_PCS_Pos 16
96 #define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos)
97 #define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
98 #define SPI_TDR_LASTXFER (0x1u << 24)
99 /* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
100 #define SPI_SR_RDRF (0x1u << 0)
101 #define SPI_SR_TDRE (0x1u << 1)
102 #define SPI_SR_MODF (0x1u << 2)
103 #define SPI_SR_OVRES (0x1u << 3)
104 #define SPI_SR_ENDRX (0x1u << 4)
105 #define SPI_SR_ENDTX (0x1u << 5)
106 #define SPI_SR_RXBUFF (0x1u << 6)
107 #define SPI_SR_TXBUFE (0x1u << 7)
108 #define SPI_SR_NSSR (0x1u << 8)
109 #define SPI_SR_TXEMPTY (0x1u << 9)
110 #define SPI_SR_UNDES (0x1u << 10)
111 #define SPI_SR_SPIENS (0x1u << 16)
112 /* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
113 #define SPI_IER_RDRF (0x1u << 0)
114 #define SPI_IER_TDRE (0x1u << 1)
115 #define SPI_IER_MODF (0x1u << 2)
116 #define SPI_IER_OVRES (0x1u << 3)
117 #define SPI_IER_ENDRX (0x1u << 4)
118 #define SPI_IER_ENDTX (0x1u << 5)
119 #define SPI_IER_RXBUFF (0x1u << 6)
120 #define SPI_IER_TXBUFE (0x1u << 7)
121 #define SPI_IER_NSSR (0x1u << 8)
122 #define SPI_IER_TXEMPTY (0x1u << 9)
123 #define SPI_IER_UNDES (0x1u << 10)
124 /* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
125 #define SPI_IDR_RDRF (0x1u << 0)
126 #define SPI_IDR_TDRE (0x1u << 1)
127 #define SPI_IDR_MODF (0x1u << 2)
128 #define SPI_IDR_OVRES (0x1u << 3)
129 #define SPI_IDR_ENDRX (0x1u << 4)
130 #define SPI_IDR_ENDTX (0x1u << 5)
131 #define SPI_IDR_RXBUFF (0x1u << 6)
132 #define SPI_IDR_TXBUFE (0x1u << 7)
133 #define SPI_IDR_NSSR (0x1u << 8)
134 #define SPI_IDR_TXEMPTY (0x1u << 9)
135 #define SPI_IDR_UNDES (0x1u << 10)
136 /* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
137 #define SPI_IMR_RDRF (0x1u << 0)
138 #define SPI_IMR_TDRE (0x1u << 1)
139 #define SPI_IMR_MODF (0x1u << 2)
140 #define SPI_IMR_OVRES (0x1u << 3)
141 #define SPI_IMR_ENDRX (0x1u << 4)
142 #define SPI_IMR_ENDTX (0x1u << 5)
143 #define SPI_IMR_RXBUFF (0x1u << 6)
144 #define SPI_IMR_TXBUFE (0x1u << 7)
145 #define SPI_IMR_NSSR (0x1u << 8)
146 #define SPI_IMR_TXEMPTY (0x1u << 9)
147 #define SPI_IMR_UNDES (0x1u << 10)
148 /* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
149 #define SPI_CSR_CPOL (0x1u << 0)
150 #define SPI_CSR_NCPHA (0x1u << 1)
151 #define SPI_CSR_CSNAAT (0x1u << 2)
152 #define SPI_CSR_CSAAT (0x1u << 3)
153 #define SPI_CSR_BITS_Pos 4
154 #define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos)
155 #define SPI_CSR_BITS_8_BIT (0x0u << 4)
156 #define SPI_CSR_BITS_9_BIT (0x1u << 4)
157 #define SPI_CSR_BITS_10_BIT (0x2u << 4)
158 #define SPI_CSR_BITS_11_BIT (0x3u << 4)
159 #define SPI_CSR_BITS_12_BIT (0x4u << 4)
160 #define SPI_CSR_BITS_13_BIT (0x5u << 4)
161 #define SPI_CSR_BITS_14_BIT (0x6u << 4)
162 #define SPI_CSR_BITS_15_BIT (0x7u << 4)
163 #define SPI_CSR_BITS_16_BIT (0x8u << 4)
164 #define SPI_CSR_SCBR_Pos 8
165 #define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos)
166 #define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
167 #define SPI_CSR_DLYBS_Pos 16
168 #define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos)
169 #define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
170 #define SPI_CSR_DLYBCT_Pos 24
171 #define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos)
172 #define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
173 /* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
174 #define SPI_WPMR_WPEN (0x1u << 0)
175 #define SPI_WPMR_WPKEY_Pos 8
176 #define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos)
177 #define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))
178 /* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
179 #define SPI_WPSR_WPVS (0x1u << 0)
180 #define SPI_WPSR_WPVSRC_Pos 8
181 #define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos)
182 /* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */
183 #define SPI_RPR_RXPTR_Pos 0
184 #define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos)
185 #define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos)))
186 /* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */
187 #define SPI_RCR_RXCTR_Pos 0
188 #define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos)
189 #define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos)))
190 /* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */
191 #define SPI_TPR_TXPTR_Pos 0
192 #define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos)
193 #define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos)))
194 /* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */
195 #define SPI_TCR_TXCTR_Pos 0
196 #define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos)
197 #define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos)))
198 /* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */
199 #define SPI_RNPR_RXNPTR_Pos 0
200 #define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos)
201 #define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos)))
202 /* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */
203 #define SPI_RNCR_RXNCTR_Pos 0
204 #define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos)
205 #define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos)))
206 /* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */
207 #define SPI_TNPR_TXNPTR_Pos 0
208 #define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos)
209 #define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos)))
210 /* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */
211 #define SPI_TNCR_TXNCTR_Pos 0
212 #define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos)
213 #define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos)))
214 /* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */
215 #define SPI_PTCR_RXTEN (0x1u << 0)
216 #define SPI_PTCR_RXTDIS (0x1u << 1)
217 #define SPI_PTCR_TXTEN (0x1u << 8)
218 #define SPI_PTCR_TXTDIS (0x1u << 9)
219 /* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */
220 #define SPI_PTSR_RXTEN (0x1u << 0)
221 #define SPI_PTSR_TXTEN (0x1u << 8)
224 
225 
226 #endif /* _SAM3S8_SPI_COMPONENT_ */
volatile uint32_t RwReg
Definition: sam3n00a.h:54
volatile uint32_t WoReg
Definition: sam3n00a.h:53
Spi hardware registers.
Definition: component_spi.h:41
volatile const uint32_t RoReg
Definition: sam3n00a.h:49