component_spi.h

/* ----------------------------------------------------------------------------
 *         SAM Software Package License
 * ----------------------------------------------------------------------------
 * Copyright (c) 2012, Atmel Corporation
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following condition is met:
 *
 * - Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the disclaimer below.
 *
 * Atmel's name may not be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * ----------------------------------------------------------------------------
 */

#ifndef _SAM4S_SPI_COMPONENT_
#define _SAM4S_SPI_COMPONENT_

/* ============================================================================= */
/* ============================================================================= */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {
  WoReg SPI_CR;        
  RwReg SPI_MR;        
  RoReg SPI_RDR;       
  WoReg SPI_TDR;       
  RoReg SPI_SR;        
  WoReg SPI_IER;       
  WoReg SPI_IDR;       
  RoReg SPI_IMR;       
  RoReg Reserved1[4];
  RwReg SPI_CSR[4];    
  RoReg Reserved2[41];
  RwReg SPI_WPMR;      
  RoReg SPI_WPSR;      
  RoReg Reserved3[5];
  RwReg SPI_RPR;       
  RwReg SPI_RCR;       
  RwReg SPI_TPR;       
  RwReg SPI_TCR;       
  RwReg SPI_RNPR;      
  RwReg SPI_RNCR;      
  RwReg SPI_TNPR;      
  RwReg SPI_TNCR;      
  WoReg SPI_PTCR;      
  RoReg SPI_PTSR;      
} Spi;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
#define SPI_CR_SPIEN (0x1u << 0) 
#define SPI_CR_SPIDIS (0x1u << 1) 
#define SPI_CR_SWRST (0x1u << 7) 
#define SPI_CR_LASTXFER (0x1u << 24) 
/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
#define SPI_MR_MSTR (0x1u << 0) 
#define SPI_MR_PS (0x1u << 1) 
#define SPI_MR_PCSDEC (0x1u << 2) 
#define SPI_MR_MODFDIS (0x1u << 4) 
#define SPI_MR_WDRBT (0x1u << 5) 
#define SPI_MR_LLB (0x1u << 7) 
#define SPI_MR_PCS_Pos 16
#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) 
#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
#define SPI_MR_DLYBCS_Pos 24
#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) 
#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
#define SPI_RDR_RD_Pos 0
#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) 
#define SPI_RDR_PCS_Pos 16
#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) 
/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
#define SPI_TDR_TD_Pos 0
#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) 
#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
#define SPI_TDR_PCS_Pos 16
#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) 
#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
#define SPI_TDR_LASTXFER (0x1u << 24) 
/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
#define SPI_SR_RDRF (0x1u << 0) 
#define SPI_SR_TDRE (0x1u << 1) 
#define SPI_SR_MODF (0x1u << 2) 
#define SPI_SR_OVRES (0x1u << 3) 
#define SPI_SR_ENDRX (0x1u << 4) 
#define SPI_SR_ENDTX (0x1u << 5) 
#define SPI_SR_RXBUFF (0x1u << 6) 
#define SPI_SR_TXBUFE (0x1u << 7) 
#define SPI_SR_NSSR (0x1u << 8) 
#define SPI_SR_TXEMPTY (0x1u << 9) 
#define SPI_SR_UNDES (0x1u << 10) 
#define SPI_SR_SPIENS (0x1u << 16) 
/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
#define SPI_IER_RDRF (0x1u << 0) 
#define SPI_IER_TDRE (0x1u << 1) 
#define SPI_IER_MODF (0x1u << 2) 
#define SPI_IER_OVRES (0x1u << 3) 
#define SPI_IER_ENDRX (0x1u << 4) 
#define SPI_IER_ENDTX (0x1u << 5) 
#define SPI_IER_RXBUFF (0x1u << 6) 
#define SPI_IER_TXBUFE (0x1u << 7) 
#define SPI_IER_NSSR (0x1u << 8) 
#define SPI_IER_TXEMPTY (0x1u << 9) 
#define SPI_IER_UNDES (0x1u << 10) 
/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
#define SPI_IDR_RDRF (0x1u << 0) 
#define SPI_IDR_TDRE (0x1u << 1) 
#define SPI_IDR_MODF (0x1u << 2) 
#define SPI_IDR_OVRES (0x1u << 3) 
#define SPI_IDR_ENDRX (0x1u << 4) 
#define SPI_IDR_ENDTX (0x1u << 5) 
#define SPI_IDR_RXBUFF (0x1u << 6) 
#define SPI_IDR_TXBUFE (0x1u << 7) 
#define SPI_IDR_NSSR (0x1u << 8) 
#define SPI_IDR_TXEMPTY (0x1u << 9) 
#define SPI_IDR_UNDES (0x1u << 10) 
/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
#define SPI_IMR_RDRF (0x1u << 0) 
#define SPI_IMR_TDRE (0x1u << 1) 
#define SPI_IMR_MODF (0x1u << 2) 
#define SPI_IMR_OVRES (0x1u << 3) 
#define SPI_IMR_ENDRX (0x1u << 4) 
#define SPI_IMR_ENDTX (0x1u << 5) 
#define SPI_IMR_RXBUFF (0x1u << 6) 
#define SPI_IMR_TXBUFE (0x1u << 7) 
#define SPI_IMR_NSSR (0x1u << 8) 
#define SPI_IMR_TXEMPTY (0x1u << 9) 
#define SPI_IMR_UNDES (0x1u << 10) 
/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
#define SPI_CSR_CPOL (0x1u << 0) 
#define SPI_CSR_NCPHA (0x1u << 1) 
#define SPI_CSR_CSNAAT (0x1u << 2) 
#define SPI_CSR_CSAAT (0x1u << 3) 
#define SPI_CSR_BITS_Pos 4
#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) 
#define   SPI_CSR_BITS_8_BIT (0x0u << 4) 
#define   SPI_CSR_BITS_9_BIT (0x1u << 4) 
#define   SPI_CSR_BITS_10_BIT (0x2u << 4) 
#define   SPI_CSR_BITS_11_BIT (0x3u << 4) 
#define   SPI_CSR_BITS_12_BIT (0x4u << 4) 
#define   SPI_CSR_BITS_13_BIT (0x5u << 4) 
#define   SPI_CSR_BITS_14_BIT (0x6u << 4) 
#define   SPI_CSR_BITS_15_BIT (0x7u << 4) 
#define   SPI_CSR_BITS_16_BIT (0x8u << 4) 
#define SPI_CSR_SCBR_Pos 8
#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) 
#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
#define SPI_CSR_DLYBS_Pos 16
#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) 
#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
#define SPI_CSR_DLYBCT_Pos 24
#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) 
#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
#define SPI_WPMR_WPEN (0x1u << 0) 
#define SPI_WPMR_WPKEY_Pos 8
#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) 
#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))
/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
#define SPI_WPSR_WPVS (0x1u << 0) 
#define SPI_WPSR_WPVSRC_Pos 8
#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) 
/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */
#define SPI_RPR_RXPTR_Pos 0
#define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos) 
#define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos)))
/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */
#define SPI_RCR_RXCTR_Pos 0
#define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos) 
#define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos)))
/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */
#define SPI_TPR_TXPTR_Pos 0
#define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos) 
#define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos)))
/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */
#define SPI_TCR_TXCTR_Pos 0
#define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos) 
#define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos)))
/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */
#define SPI_RNPR_RXNPTR_Pos 0
#define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos) 
#define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos)))
/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */
#define SPI_RNCR_RXNCTR_Pos 0
#define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos) 
#define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos)))
/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */
#define SPI_TNPR_TXNPTR_Pos 0
#define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos) 
#define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos)))
/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */
#define SPI_TNCR_TXNCTR_Pos 0
#define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos) 
#define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos)))
/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */
#define SPI_PTCR_RXTEN (0x1u << 0) 
#define SPI_PTCR_RXTDIS (0x1u << 1) 
#define SPI_PTCR_TXTEN (0x1u << 8) 
#define SPI_PTCR_TXTDIS (0x1u << 9) 
/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */
#define SPI_PTSR_RXTEN (0x1u << 0) 
#define SPI_PTSR_TXTEN (0x1u << 8) 


#endif /* _SAM4S_SPI_COMPONENT_ */