component_supc.h

/* ----------------------------------------------------------------------------
 *         SAM Software Package License
 * ----------------------------------------------------------------------------
 * Copyright (c) 2012, Atmel Corporation
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following condition is met:
 *
 * - Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the disclaimer below.
 *
 * Atmel's name may not be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * ----------------------------------------------------------------------------
 */

#ifndef _SAM3S8_SUPC_COMPONENT_
#define _SAM3S8_SUPC_COMPONENT_

/* ============================================================================= */
/* ============================================================================= */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {
  WoReg SUPC_CR;   
  RwReg SUPC_SMMR; 
  RwReg SUPC_MR;   
  RwReg SUPC_WUMR; 
  RwReg SUPC_WUIR; 
  RoReg SUPC_SR;   
} Supc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
#define SUPC_CR_VROFF (0x1u << 2) 
#define   SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) 
#define   SUPC_CR_VROFF_STOP_VREG (0x1u << 2) 
#define SUPC_CR_XTALSEL (0x1u << 3) 
#define   SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) 
#define   SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) 
#define SUPC_CR_KEY_Pos 24
#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) 
#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
#define SUPC_SMMR_SMTH_Pos 0
#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) 
#define   SUPC_SMMR_SMTH_1_9V (0x0u << 0) 
#define   SUPC_SMMR_SMTH_2_0V (0x1u << 0) 
#define   SUPC_SMMR_SMTH_2_1V (0x2u << 0) 
#define   SUPC_SMMR_SMTH_2_2V (0x3u << 0) 
#define   SUPC_SMMR_SMTH_2_3V (0x4u << 0) 
#define   SUPC_SMMR_SMTH_2_4V (0x5u << 0) 
#define   SUPC_SMMR_SMTH_2_5V (0x6u << 0) 
#define   SUPC_SMMR_SMTH_2_6V (0x7u << 0) 
#define   SUPC_SMMR_SMTH_2_7V (0x8u << 0) 
#define   SUPC_SMMR_SMTH_2_8V (0x9u << 0) 
#define   SUPC_SMMR_SMTH_2_9V (0xAu << 0) 
#define   SUPC_SMMR_SMTH_3_0V (0xBu << 0) 
#define   SUPC_SMMR_SMTH_3_1V (0xCu << 0) 
#define   SUPC_SMMR_SMTH_3_2V (0xDu << 0) 
#define   SUPC_SMMR_SMTH_3_3V (0xEu << 0) 
#define   SUPC_SMMR_SMTH_3_4V (0xFu << 0) 
#define SUPC_SMMR_SMSMPL_Pos 8
#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) 
#define   SUPC_SMMR_SMSMPL_SMD (0x0u << 8) 
#define   SUPC_SMMR_SMSMPL_CSM (0x1u << 8) 
#define   SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) 
#define   SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) 
#define   SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) 
#define SUPC_SMMR_SMRSTEN (0x1u << 12) 
#define   SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) 
#define   SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) 
#define SUPC_SMMR_SMIEN (0x1u << 13) 
#define   SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) 
#define   SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) 
/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
#define SUPC_MR_BODRSTEN (0x1u << 12) 
#define   SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) 
#define   SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) 
#define SUPC_MR_BODDIS (0x1u << 13) 
#define   SUPC_MR_BODDIS_ENABLE (0x0u << 13) 
#define   SUPC_MR_BODDIS_DISABLE (0x1u << 13) 
#define SUPC_MR_ONREG (0x1u << 14) 
#define   SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) 
#define   SUPC_MR_ONREG_ONREG_USED (0x1u << 14) 
#define SUPC_MR_OSCBYPASS (0x1u << 20) 
#define   SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) 
#define   SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) 
#define SUPC_MR_KEY_Pos 24
#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) 
#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
#define SUPC_WUMR_SMEN (0x1u << 1) 
#define   SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) 
#define   SUPC_WUMR_SMEN_ENABLE (0x1u << 1) 
#define SUPC_WUMR_RTTEN (0x1u << 2) 
#define   SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) 
#define   SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) 
#define SUPC_WUMR_RTCEN (0x1u << 3) 
#define   SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) 
#define   SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) 
#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) 
#define   SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) 
#define   SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) 
#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) 
#define   SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) 
#define   SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) 
#define SUPC_WUMR_LPDBCCLR (0x1u << 7) 
#define   SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) 
#define   SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) 
#define SUPC_WUMR_WKUPDBC_Pos 12
#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) 
#define   SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) 
#define   SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) 
#define   SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) 
#define   SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) 
#define   SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) 
#define   SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) 
#define SUPC_WUMR_LPDBC_Pos 16
#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) 
#define   SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) 
#define   SUPC_WUMR_LPDBC_2_RTCOUT0 (0x1u << 16) 
#define   SUPC_WUMR_LPDBC_3_RTCOUT0 (0x2u << 16) 
#define   SUPC_WUMR_LPDBC_4_RTCOUT0 (0x3u << 16) 
#define   SUPC_WUMR_LPDBC_5_RTCOUT0 (0x4u << 16) 
#define   SUPC_WUMR_LPDBC_6_RTCOUT0 (0x5u << 16) 
#define   SUPC_WUMR_LPDBC_7_RTCOUT0 (0x6u << 16) 
#define   SUPC_WUMR_LPDBC_8_RTCOUT0 (0x7u << 16) 
/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
#define SUPC_WUIR_WKUPEN0 (0x1u << 0) 
#define   SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) 
#define   SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) 
#define SUPC_WUIR_WKUPEN1 (0x1u << 1) 
#define   SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) 
#define   SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) 
#define SUPC_WUIR_WKUPEN2 (0x1u << 2) 
#define   SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) 
#define   SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) 
#define SUPC_WUIR_WKUPEN3 (0x1u << 3) 
#define   SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) 
#define   SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) 
#define SUPC_WUIR_WKUPEN4 (0x1u << 4) 
#define   SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) 
#define   SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) 
#define SUPC_WUIR_WKUPEN5 (0x1u << 5) 
#define   SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) 
#define   SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) 
#define SUPC_WUIR_WKUPEN6 (0x1u << 6) 
#define   SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) 
#define   SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) 
#define SUPC_WUIR_WKUPEN7 (0x1u << 7) 
#define   SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) 
#define   SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) 
#define SUPC_WUIR_WKUPEN8 (0x1u << 8) 
#define   SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) 
#define   SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) 
#define SUPC_WUIR_WKUPEN9 (0x1u << 9) 
#define   SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) 
#define   SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) 
#define SUPC_WUIR_WKUPEN10 (0x1u << 10) 
#define   SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) 
#define   SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) 
#define SUPC_WUIR_WKUPEN11 (0x1u << 11) 
#define   SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) 
#define   SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) 
#define SUPC_WUIR_WKUPEN12 (0x1u << 12) 
#define   SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) 
#define   SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) 
#define SUPC_WUIR_WKUPEN13 (0x1u << 13) 
#define   SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) 
#define   SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) 
#define SUPC_WUIR_WKUPEN14 (0x1u << 14) 
#define   SUPC_WUIR_WKUPEN14_DISABLE (0x0u << 14) 
#define   SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) 
#define SUPC_WUIR_WKUPEN15 (0x1u << 15) 
#define   SUPC_WUIR_WKUPEN15_DISABLE (0x0u << 15) 
#define   SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) 
#define SUPC_WUIR_WKUPT0 (0x1u << 16) 
#define   SUPC_WUIR_WKUPT0_LOW (0x0u << 16) 
#define   SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) 
#define SUPC_WUIR_WKUPT1 (0x1u << 17) 
#define   SUPC_WUIR_WKUPT1_LOW (0x0u << 17) 
#define   SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) 
#define SUPC_WUIR_WKUPT2 (0x1u << 18) 
#define   SUPC_WUIR_WKUPT2_LOW (0x0u << 18) 
#define   SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) 
#define SUPC_WUIR_WKUPT3 (0x1u << 19) 
#define   SUPC_WUIR_WKUPT3_LOW (0x0u << 19) 
#define   SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) 
#define SUPC_WUIR_WKUPT4 (0x1u << 20) 
#define   SUPC_WUIR_WKUPT4_LOW (0x0u << 20) 
#define   SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) 
#define SUPC_WUIR_WKUPT5 (0x1u << 21) 
#define   SUPC_WUIR_WKUPT5_LOW (0x0u << 21) 
#define   SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) 
#define SUPC_WUIR_WKUPT6 (0x1u << 22) 
#define   SUPC_WUIR_WKUPT6_LOW (0x0u << 22) 
#define   SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) 
#define SUPC_WUIR_WKUPT7 (0x1u << 23) 
#define   SUPC_WUIR_WKUPT7_LOW (0x0u << 23) 
#define   SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) 
#define SUPC_WUIR_WKUPT8 (0x1u << 24) 
#define   SUPC_WUIR_WKUPT8_LOW (0x0u << 24) 
#define   SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) 
#define SUPC_WUIR_WKUPT9 (0x1u << 25) 
#define   SUPC_WUIR_WKUPT9_LOW (0x0u << 25) 
#define   SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) 
#define SUPC_WUIR_WKUPT10 (0x1u << 26) 
#define   SUPC_WUIR_WKUPT10_LOW (0x0u << 26) 
#define   SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) 
#define SUPC_WUIR_WKUPT11 (0x1u << 27) 
#define   SUPC_WUIR_WKUPT11_LOW (0x0u << 27) 
#define   SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) 
#define SUPC_WUIR_WKUPT12 (0x1u << 28) 
#define   SUPC_WUIR_WKUPT12_LOW (0x0u << 28) 
#define   SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) 
#define SUPC_WUIR_WKUPT13 (0x1u << 29) 
#define   SUPC_WUIR_WKUPT13_LOW (0x0u << 29) 
#define   SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) 
#define SUPC_WUIR_WKUPT14 (0x1u << 30) 
#define   SUPC_WUIR_WKUPT14_LOW (0x0u << 30) 
#define   SUPC_WUIR_WKUPT14_HIGH (0x1u << 30) 
#define SUPC_WUIR_WKUPT15 (0x1u << 31) 
#define   SUPC_WUIR_WKUPT15_LOW (0x0u << 31) 
#define   SUPC_WUIR_WKUPT15_HIGH (0x1u << 31) 
/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
#define SUPC_SR_WKUPS (0x1u << 1) 
#define   SUPC_SR_WKUPS_NO (0x0u << 1) 
#define   SUPC_SR_WKUPS_PRESENT (0x1u << 1) 
#define SUPC_SR_SMWS (0x1u << 2) 
#define   SUPC_SR_SMWS_NO (0x0u << 2) 
#define   SUPC_SR_SMWS_PRESENT (0x1u << 2) 
#define SUPC_SR_BODRSTS (0x1u << 3) 
#define   SUPC_SR_BODRSTS_NO (0x0u << 3) 
#define   SUPC_SR_BODRSTS_PRESENT (0x1u << 3) 
#define SUPC_SR_SMRSTS (0x1u << 4) 
#define   SUPC_SR_SMRSTS_NO (0x0u << 4) 
#define   SUPC_SR_SMRSTS_PRESENT (0x1u << 4) 
#define SUPC_SR_SMS (0x1u << 5) 
#define   SUPC_SR_SMS_NO (0x0u << 5) 
#define   SUPC_SR_SMS_PRESENT (0x1u << 5) 
#define SUPC_SR_SMOS (0x1u << 6) 
#define   SUPC_SR_SMOS_HIGH (0x0u << 6) 
#define   SUPC_SR_SMOS_LOW (0x1u << 6) 
#define SUPC_SR_OSCSEL (0x1u << 7) 
#define   SUPC_SR_OSCSEL_RC (0x0u << 7) 
#define   SUPC_SR_OSCSEL_CRYST (0x1u << 7) 
#define SUPC_SR_LPDBCS0 (0x1u << 13) 
#define   SUPC_SR_LPDBCS0_NO (0x0u << 13) 
#define   SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) 
#define SUPC_SR_LPDBCS1 (0x1u << 14) 
#define   SUPC_SR_LPDBCS1_NO (0x0u << 14) 
#define   SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) 
#define SUPC_SR_WKUPIS0 (0x1u << 16) 
#define   SUPC_SR_WKUPIS0_DIS (0x0u << 16) 
#define   SUPC_SR_WKUPIS0_EN (0x1u << 16) 
#define SUPC_SR_WKUPIS1 (0x1u << 17) 
#define   SUPC_SR_WKUPIS1_DIS (0x0u << 17) 
#define   SUPC_SR_WKUPIS1_EN (0x1u << 17) 
#define SUPC_SR_WKUPIS2 (0x1u << 18) 
#define   SUPC_SR_WKUPIS2_DIS (0x0u << 18) 
#define   SUPC_SR_WKUPIS2_EN (0x1u << 18) 
#define SUPC_SR_WKUPIS3 (0x1u << 19) 
#define   SUPC_SR_WKUPIS3_DIS (0x0u << 19) 
#define   SUPC_SR_WKUPIS3_EN (0x1u << 19) 
#define SUPC_SR_WKUPIS4 (0x1u << 20) 
#define   SUPC_SR_WKUPIS4_DIS (0x0u << 20) 
#define   SUPC_SR_WKUPIS4_EN (0x1u << 20) 
#define SUPC_SR_WKUPIS5 (0x1u << 21) 
#define   SUPC_SR_WKUPIS5_DIS (0x0u << 21) 
#define   SUPC_SR_WKUPIS5_EN (0x1u << 21) 
#define SUPC_SR_WKUPIS6 (0x1u << 22) 
#define   SUPC_SR_WKUPIS6_DIS (0x0u << 22) 
#define   SUPC_SR_WKUPIS6_EN (0x1u << 22) 
#define SUPC_SR_WKUPIS7 (0x1u << 23) 
#define   SUPC_SR_WKUPIS7_DIS (0x0u << 23) 
#define   SUPC_SR_WKUPIS7_EN (0x1u << 23) 
#define SUPC_SR_WKUPIS8 (0x1u << 24) 
#define   SUPC_SR_WKUPIS8_DIS (0x0u << 24) 
#define   SUPC_SR_WKUPIS8_EN (0x1u << 24) 
#define SUPC_SR_WKUPIS9 (0x1u << 25) 
#define   SUPC_SR_WKUPIS9_DIS (0x0u << 25) 
#define   SUPC_SR_WKUPIS9_EN (0x1u << 25) 
#define SUPC_SR_WKUPIS10 (0x1u << 26) 
#define   SUPC_SR_WKUPIS10_DIS (0x0u << 26) 
#define   SUPC_SR_WKUPIS10_EN (0x1u << 26) 
#define SUPC_SR_WKUPIS11 (0x1u << 27) 
#define   SUPC_SR_WKUPIS11_DIS (0x0u << 27) 
#define   SUPC_SR_WKUPIS11_EN (0x1u << 27) 
#define SUPC_SR_WKUPIS12 (0x1u << 28) 
#define   SUPC_SR_WKUPIS12_DIS (0x0u << 28) 
#define   SUPC_SR_WKUPIS12_EN (0x1u << 28) 
#define SUPC_SR_WKUPIS13 (0x1u << 29) 
#define   SUPC_SR_WKUPIS13_DIS (0x0u << 29) 
#define   SUPC_SR_WKUPIS13_EN (0x1u << 29) 
#define SUPC_SR_WKUPIS14 (0x1u << 30) 
#define   SUPC_SR_WKUPIS14_DIS (0x0u << 30) 
#define   SUPC_SR_WKUPIS14_EN (0x1u << 30) 
#define SUPC_SR_WKUPIS15 (0x1u << 31) 
#define   SUPC_SR_WKUPIS15_DIS (0x0u << 31) 
#define   SUPC_SR_WKUPIS15_EN (0x1u << 31) 


#endif /* _SAM3S8_SUPC_COMPONENT_ */