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#define | SUPC_CR_VROFF (0x1u << 2) |
| | (SUPC_CR) Voltage Regulator Off
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#define | SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) |
| | (SUPC_CR) no effect.
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#define | SUPC_CR_VROFF_STOP_VREG (0x1u << 2) |
| | (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator.
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#define | SUPC_CR_XTALSEL (0x1u << 3) |
| | (SUPC_CR) Crystal Oscillator Select
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#define | SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) |
| | (SUPC_CR) no effect.
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#define | SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) |
| | (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output.
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#define | SUPC_CR_KEY_Pos 24 |
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#define | SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) |
| | (SUPC_CR) Password
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#define | SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos))) |
| |
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#define | SUPC_SMMR_SMTH_Pos 0 |
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#define | SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) |
| | (SUPC_SMMR) Supply Monitor Threshold
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#define | SUPC_SMMR_SMTH_1_9V (0x0u << 0) |
| | (SUPC_SMMR) 1.9 V
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#define | SUPC_SMMR_SMTH_2_0V (0x1u << 0) |
| | (SUPC_SMMR) 2.0 V
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#define | SUPC_SMMR_SMTH_2_1V (0x2u << 0) |
| | (SUPC_SMMR) 2.1 V
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#define | SUPC_SMMR_SMTH_2_2V (0x3u << 0) |
| | (SUPC_SMMR) 2.2 V
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#define | SUPC_SMMR_SMTH_2_3V (0x4u << 0) |
| | (SUPC_SMMR) 2.3 V
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#define | SUPC_SMMR_SMTH_2_4V (0x5u << 0) |
| | (SUPC_SMMR) 2.4 V
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#define | SUPC_SMMR_SMTH_2_5V (0x6u << 0) |
| | (SUPC_SMMR) 2.5 V
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#define | SUPC_SMMR_SMTH_2_6V (0x7u << 0) |
| | (SUPC_SMMR) 2.6 V
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#define | SUPC_SMMR_SMTH_2_7V (0x8u << 0) |
| | (SUPC_SMMR) 2.7 V
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#define | SUPC_SMMR_SMTH_2_8V (0x9u << 0) |
| | (SUPC_SMMR) 2.8 V
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#define | SUPC_SMMR_SMTH_2_9V (0xAu << 0) |
| | (SUPC_SMMR) 2.9 V
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#define | SUPC_SMMR_SMTH_3_0V (0xBu << 0) |
| | (SUPC_SMMR) 3.0 V
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#define | SUPC_SMMR_SMTH_3_1V (0xCu << 0) |
| | (SUPC_SMMR) 3.1 V
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#define | SUPC_SMMR_SMTH_3_2V (0xDu << 0) |
| | (SUPC_SMMR) 3.2 V
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#define | SUPC_SMMR_SMTH_3_3V (0xEu << 0) |
| | (SUPC_SMMR) 3.3 V
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#define | SUPC_SMMR_SMTH_3_4V (0xFu << 0) |
| | (SUPC_SMMR) 3.4 V
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#define | SUPC_SMMR_SMSMPL_Pos 8 |
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#define | SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) |
| | (SUPC_SMMR) Supply Monitor Sampling Period
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#define | SUPC_SMMR_SMSMPL_SMD (0x0u << 8) |
| | (SUPC_SMMR) Supply Monitor disabled
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#define | SUPC_SMMR_SMSMPL_CSM (0x1u << 8) |
| | (SUPC_SMMR) Continuous Supply Monitor
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#define | SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) |
| | (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods
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#define | SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) |
| | (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods
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#define | SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) |
| | (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods
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#define | SUPC_SMMR_SMRSTEN (0x1u << 12) |
| | (SUPC_SMMR) Supply Monitor Reset Enable
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#define | SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) |
| | (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs.
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#define | SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) |
| | (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs.
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#define | SUPC_SMMR_SMIEN (0x1u << 13) |
| | (SUPC_SMMR) Supply Monitor Interrupt Enable
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#define | SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) |
| | (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs.
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#define | SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) |
| | (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs.
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#define | SUPC_MR_BODRSTEN (0x1u << 12) |
| | (SUPC_MR) Brownout Detector Reset Enable
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#define | SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) |
| | (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs.
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#define | SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) |
| | (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs.
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#define | SUPC_MR_BODDIS (0x1u << 13) |
| | (SUPC_MR) Brownout Detector Disable
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#define | SUPC_MR_BODDIS_ENABLE (0x0u << 13) |
| | (SUPC_MR) the core brownout detector is enabled.
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#define | SUPC_MR_BODDIS_DISABLE (0x1u << 13) |
| | (SUPC_MR) the core brownout detector is disabled.
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#define | SUPC_MR_ONREG (0x1u << 14) |
| | (SUPC_MR) Voltage Regulator enable
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#define | SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) |
| | (SUPC_MR) Voltage Regulator is not used
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#define | SUPC_MR_ONREG_ONREG_USED (0x1u << 14) |
| | (SUPC_MR) Voltage Regulator is used
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#define | SUPC_MR_OSCBYPASS (0x1u << 20) |
| | (SUPC_MR) Oscillator Bypass
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#define | SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) |
| | (SUPC_MR) no effect. Clock selection depends on XTALSEL value.
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#define | SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) |
| | (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode.
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#define | SUPC_MR_KEY_Pos 24 |
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#define | SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) |
| | (SUPC_MR) Password Key
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#define | SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos))) |
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#define | SUPC_WUMR_SMEN (0x1u << 1) |
| | (SUPC_WUMR) Supply Monitor Wake Up Enable
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#define | SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) |
| | (SUPC_WUMR) the supply monitor detection has no wake up effect.
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#define | SUPC_WUMR_SMEN_ENABLE (0x1u << 1) |
| | (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply.
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#define | SUPC_WUMR_RTTEN (0x1u << 2) |
| | (SUPC_WUMR) Real Time Timer Wake Up Enable
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#define | SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) |
| | (SUPC_WUMR) the RTT alarm signal has no wake up effect.
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#define | SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) |
| | (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply.
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#define | SUPC_WUMR_RTCEN (0x1u << 3) |
| | (SUPC_WUMR) Real Time Clock Wake Up Enable
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#define | SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) |
| | (SUPC_WUMR) the RTC alarm signal has no wake up effect.
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#define | SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) |
| | (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply.
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#define | SUPC_WUMR_LPDBCEN0 (0x1u << 5) |
| | (SUPC_WUMR) Low power Debouncer ENable WKUP0
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#define | SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) |
| | (SUPC_WUMR) the WKUP0 input pin is not connected with low power debouncer.
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#define | SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) |
| | (SUPC_WUMR) the WKUP0 input pin is connected with low power debouncer and can force a core wake up.
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#define | SUPC_WUMR_LPDBCEN1 (0x1u << 6) |
| | (SUPC_WUMR) Low power Debouncer ENable WKUP1
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#define | SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) |
| | (SUPC_WUMR) the WKUP1input pin is not connected with low power debouncer.
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#define | SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) |
| | (SUPC_WUMR) the WKUP1 input pin is connected with low power debouncer and can force a core wake up.
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#define | SUPC_WUMR_LPDBCCLR (0x1u << 7) |
| | (SUPC_WUMR) Low power Debouncer Clear
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#define | SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) |
| | (SUPC_WUMR) a low power debounce event does not create an immediate clear on first half GPBR registers.
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#define | SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) |
| | (SUPC_WUMR) a low power debounce event on WKUP0 or WKUP1 generates an immediate clear on first half GPBR registers.
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#define | SUPC_WUMR_WKUPDBC_Pos 12 |
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#define | SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) |
| | (SUPC_WUMR) Wake Up Inputs Debouncer Period
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#define | SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) |
| | (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge.
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#define | SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) |
| | (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods
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#define | SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) |
| | (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods
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#define | SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) |
| | (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods
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#define | SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) |
| | (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods
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#define | SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) |
| | (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods
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#define | SUPC_WUMR_LPDBC_Pos 16 |
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#define | SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) |
| | (SUPC_WUMR) Low Power DeBounCer Period
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#define | SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) |
| | (SUPC_WUMR) Disable the low power debouncer.
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#define | SUPC_WUMR_LPDBC_2_RTCOUT0 (0x1u << 16) |
| | (SUPC_WUMR) WKUP0/1 in its active state for at least 2 RTCOUT0 periods
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#define | SUPC_WUMR_LPDBC_3_RTCOUT0 (0x2u << 16) |
| | (SUPC_WUMR) WKUP0/1 in its active state for at least 3 RTCOUT0 periods
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#define | SUPC_WUMR_LPDBC_4_RTCOUT0 (0x3u << 16) |
| | (SUPC_WUMR) WKUP0/1 in its active state for at least 4 RTCOUT0 periods
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#define | SUPC_WUMR_LPDBC_5_RTCOUT0 (0x4u << 16) |
| | (SUPC_WUMR) WKUP0/1 in its active state for at least 5 RTCOUT0 periods
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#define | SUPC_WUMR_LPDBC_6_RTCOUT0 (0x5u << 16) |
| | (SUPC_WUMR) WKUP0/1 in its active state for at least 6 RTCOUT0 periods
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#define | SUPC_WUMR_LPDBC_7_RTCOUT0 (0x6u << 16) |
| | (SUPC_WUMR) WKUP0/1 in its active state for at least 7 RTCOUT0 periods
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#define | SUPC_WUMR_LPDBC_8_RTCOUT0 (0x7u << 16) |
| | (SUPC_WUMR) WKUP0/1 in its active state for at least 8 RTCOUT0 periods
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#define | SUPC_WUIR_WKUPEN0 (0x1u << 0) |
| | (SUPC_WUIR) Wake Up Input Enable 0
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#define | SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) |
| | (SUPC_WUIR) the corresponding wake-up input has no wake up effect.
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#define | SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) |
| | (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPEN1 (0x1u << 1) |
| | (SUPC_WUIR) Wake Up Input Enable 1
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#define | SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) |
| | (SUPC_WUIR) the corresponding wake-up input has no wake up effect.
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#define | SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) |
| | (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPEN2 (0x1u << 2) |
| | (SUPC_WUIR) Wake Up Input Enable 2
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#define | SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) |
| | (SUPC_WUIR) the corresponding wake-up input has no wake up effect.
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#define | SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) |
| | (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPEN3 (0x1u << 3) |
| | (SUPC_WUIR) Wake Up Input Enable 3
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#define | SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) |
| | (SUPC_WUIR) the corresponding wake-up input has no wake up effect.
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#define | SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) |
| | (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPEN4 (0x1u << 4) |
| | (SUPC_WUIR) Wake Up Input Enable 4
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#define | SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) |
| | (SUPC_WUIR) the corresponding wake-up input has no wake up effect.
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#define | SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) |
| | (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPEN5 (0x1u << 5) |
| | (SUPC_WUIR) Wake Up Input Enable 5
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#define | SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) |
| | (SUPC_WUIR) the corresponding wake-up input has no wake up effect.
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#define | SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) |
| | (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPEN6 (0x1u << 6) |
| | (SUPC_WUIR) Wake Up Input Enable 6
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#define | SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) |
| | (SUPC_WUIR) the corresponding wake-up input has no wake up effect.
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#define | SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) |
| | (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPEN7 (0x1u << 7) |
| | (SUPC_WUIR) Wake Up Input Enable 7
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#define | SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) |
| | (SUPC_WUIR) the corresponding wake-up input has no wake up effect.
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#define | SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) |
| | (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPEN8 (0x1u << 8) |
| | (SUPC_WUIR) Wake Up Input Enable 8
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#define | SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) |
| | (SUPC_WUIR) the corresponding wake-up input has no wake up effect.
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#define | SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) |
| | (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPEN9 (0x1u << 9) |
| | (SUPC_WUIR) Wake Up Input Enable 9
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#define | SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) |
| | (SUPC_WUIR) the corresponding wake-up input has no wake up effect.
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#define | SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) |
| | (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPEN10 (0x1u << 10) |
| | (SUPC_WUIR) Wake Up Input Enable 10
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#define | SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) |
| | (SUPC_WUIR) the corresponding wake-up input has no wake up effect.
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#define | SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) |
| | (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPEN11 (0x1u << 11) |
| | (SUPC_WUIR) Wake Up Input Enable 11
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#define | SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) |
| | (SUPC_WUIR) the corresponding wake-up input has no wake up effect.
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#define | SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) |
| | (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPEN12 (0x1u << 12) |
| | (SUPC_WUIR) Wake Up Input Enable 12
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#define | SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) |
| | (SUPC_WUIR) the corresponding wake-up input has no wake up effect.
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#define | SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) |
| | (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPEN13 (0x1u << 13) |
| | (SUPC_WUIR) Wake Up Input Enable 13
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#define | SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) |
| | (SUPC_WUIR) the corresponding wake-up input has no wake up effect.
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#define | SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) |
| | (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPEN14 (0x1u << 14) |
| | (SUPC_WUIR) Wake Up Input Enable 14
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#define | SUPC_WUIR_WKUPEN14_DISABLE (0x0u << 14) |
| | (SUPC_WUIR) the corresponding wake-up input has no wake up effect.
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#define | SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) |
| | (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPEN15 (0x1u << 15) |
| | (SUPC_WUIR) Wake Up Input Enable 15
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#define | SUPC_WUIR_WKUPEN15_DISABLE (0x0u << 15) |
| | (SUPC_WUIR) the corresponding wake-up input has no wake up effect.
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#define | SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) |
| | (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT0 (0x1u << 16) |
| | (SUPC_WUIR) Wake Up Input Type 0
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#define | SUPC_WUIR_WKUPT0_LOW (0x0u << 16) |
| | (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) |
| | (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT1 (0x1u << 17) |
| | (SUPC_WUIR) Wake Up Input Type 1
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#define | SUPC_WUIR_WKUPT1_LOW (0x0u << 17) |
| | (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) |
| | (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT2 (0x1u << 18) |
| | (SUPC_WUIR) Wake Up Input Type 2
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#define | SUPC_WUIR_WKUPT2_LOW (0x0u << 18) |
| | (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) |
| | (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT3 (0x1u << 19) |
| | (SUPC_WUIR) Wake Up Input Type 3
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#define | SUPC_WUIR_WKUPT3_LOW (0x0u << 19) |
| | (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) |
| | (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT4 (0x1u << 20) |
| | (SUPC_WUIR) Wake Up Input Type 4
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#define | SUPC_WUIR_WKUPT4_LOW (0x0u << 20) |
| | (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) |
| | (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT5 (0x1u << 21) |
| | (SUPC_WUIR) Wake Up Input Type 5
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#define | SUPC_WUIR_WKUPT5_LOW (0x0u << 21) |
| | (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) |
| | (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT6 (0x1u << 22) |
| | (SUPC_WUIR) Wake Up Input Type 6
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#define | SUPC_WUIR_WKUPT6_LOW (0x0u << 22) |
| | (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) |
| | (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT7 (0x1u << 23) |
| | (SUPC_WUIR) Wake Up Input Type 7
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#define | SUPC_WUIR_WKUPT7_LOW (0x0u << 23) |
| | (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) |
| | (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT8 (0x1u << 24) |
| | (SUPC_WUIR) Wake Up Input Type 8
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#define | SUPC_WUIR_WKUPT8_LOW (0x0u << 24) |
| | (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) |
| | (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT9 (0x1u << 25) |
| | (SUPC_WUIR) Wake Up Input Type 9
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#define | SUPC_WUIR_WKUPT9_LOW (0x0u << 25) |
| | (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) |
| | (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT10 (0x1u << 26) |
| | (SUPC_WUIR) Wake Up Input Type 10
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#define | SUPC_WUIR_WKUPT10_LOW (0x0u << 26) |
| | (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) |
| | (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT11 (0x1u << 27) |
| | (SUPC_WUIR) Wake Up Input Type 11
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#define | SUPC_WUIR_WKUPT11_LOW (0x0u << 27) |
| | (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) |
| | (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT12 (0x1u << 28) |
| | (SUPC_WUIR) Wake Up Input Type 12
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#define | SUPC_WUIR_WKUPT12_LOW (0x0u << 28) |
| | (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) |
| | (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT13 (0x1u << 29) |
| | (SUPC_WUIR) Wake Up Input Type 13
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#define | SUPC_WUIR_WKUPT13_LOW (0x0u << 29) |
| | (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) |
| | (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT14 (0x1u << 30) |
| | (SUPC_WUIR) Wake Up Input Type 14
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#define | SUPC_WUIR_WKUPT14_LOW (0x0u << 30) |
| | (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT14_HIGH (0x1u << 30) |
| | (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT15 (0x1u << 31) |
| | (SUPC_WUIR) Wake Up Input Type 15
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#define | SUPC_WUIR_WKUPT15_LOW (0x0u << 31) |
| | (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply.
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#define | SUPC_WUIR_WKUPT15_HIGH (0x1u << 31) |
| | (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply.
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#define | SUPC_SR_WKUPS (0x1u << 1) |
| | (SUPC_SR) WKUP Wake Up Status
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#define | SUPC_SR_WKUPS_NO (0x0u << 1) |
| | (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
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#define | SUPC_SR_WKUPS_PRESENT (0x1u << 1) |
| | (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
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#define | SUPC_SR_SMWS (0x1u << 2) |
| | (SUPC_SR) Supply Monitor Detection Wake Up Status
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#define | SUPC_SR_SMWS_NO (0x0u << 2) |
| | (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR.
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#define | SUPC_SR_SMWS_PRESENT (0x1u << 2) |
| | (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR.
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#define | SUPC_SR_BODRSTS (0x1u << 3) |
| | (SUPC_SR) Brownout Detector Reset Status
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#define | SUPC_SR_BODRSTS_NO (0x0u << 3) |
| | (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR.
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#define | SUPC_SR_BODRSTS_PRESENT (0x1u << 3) |
| | (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR.
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#define | SUPC_SR_SMRSTS (0x1u << 4) |
| | (SUPC_SR) Supply Monitor Reset Status
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#define | SUPC_SR_SMRSTS_NO (0x0u << 4) |
| | (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR.
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#define | SUPC_SR_SMRSTS_PRESENT (0x1u << 4) |
| | (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR.
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#define | SUPC_SR_SMS (0x1u << 5) |
| | (SUPC_SR) Supply Monitor Status
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#define | SUPC_SR_SMS_NO (0x0u << 5) |
| | (SUPC_SR) no supply monitor detection since the last read of SUPC_SR.
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#define | SUPC_SR_SMS_PRESENT (0x1u << 5) |
| | (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR.
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#define | SUPC_SR_SMOS (0x1u << 6) |
| | (SUPC_SR) Supply Monitor Output Status
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#define | SUPC_SR_SMOS_HIGH (0x0u << 6) |
| | (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement.
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#define | SUPC_SR_SMOS_LOW (0x1u << 6) |
| | (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement.
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#define | SUPC_SR_OSCSEL (0x1u << 7) |
| | (SUPC_SR) 32-kHz Oscillator Selection Status
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#define | SUPC_SR_OSCSEL_RC (0x0u << 7) |
| | (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator.
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#define | SUPC_SR_OSCSEL_CRYST (0x1u << 7) |
| | (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator.
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#define | SUPC_SR_LPDBCS0 (0x1u << 13) |
| | (SUPC_SR) Low Power Debouncer Wake Up Status on WKUP0
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#define | SUPC_SR_LPDBCS0_NO (0x0u << 13) |
| | (SUPC_SR) no wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.
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#define | SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) |
| | (SUPC_SR) at least one wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.
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#define | SUPC_SR_LPDBCS1 (0x1u << 14) |
| | (SUPC_SR) Low Power Debouncer Wake Up Status on WKUP1
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#define | SUPC_SR_LPDBCS1_NO (0x0u << 14) |
| | (SUPC_SR) no wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.
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#define | SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) |
| | (SUPC_SR) at least one wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.
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#define | SUPC_SR_WKUPIS0 (0x1u << 16) |
| | (SUPC_SR) WKUP Input Status 0
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#define | SUPC_SR_WKUPIS0_DIS (0x0u << 16) |
| | (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS0_EN (0x1u << 16) |
| | (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS1 (0x1u << 17) |
| | (SUPC_SR) WKUP Input Status 1
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#define | SUPC_SR_WKUPIS1_DIS (0x0u << 17) |
| | (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS1_EN (0x1u << 17) |
| | (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS2 (0x1u << 18) |
| | (SUPC_SR) WKUP Input Status 2
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#define | SUPC_SR_WKUPIS2_DIS (0x0u << 18) |
| | (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS2_EN (0x1u << 18) |
| | (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS3 (0x1u << 19) |
| | (SUPC_SR) WKUP Input Status 3
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#define | SUPC_SR_WKUPIS3_DIS (0x0u << 19) |
| | (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS3_EN (0x1u << 19) |
| | (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS4 (0x1u << 20) |
| | (SUPC_SR) WKUP Input Status 4
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#define | SUPC_SR_WKUPIS4_DIS (0x0u << 20) |
| | (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS4_EN (0x1u << 20) |
| | (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS5 (0x1u << 21) |
| | (SUPC_SR) WKUP Input Status 5
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#define | SUPC_SR_WKUPIS5_DIS (0x0u << 21) |
| | (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS5_EN (0x1u << 21) |
| | (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS6 (0x1u << 22) |
| | (SUPC_SR) WKUP Input Status 6
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#define | SUPC_SR_WKUPIS6_DIS (0x0u << 22) |
| | (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS6_EN (0x1u << 22) |
| | (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS7 (0x1u << 23) |
| | (SUPC_SR) WKUP Input Status 7
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#define | SUPC_SR_WKUPIS7_DIS (0x0u << 23) |
| | (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS7_EN (0x1u << 23) |
| | (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS8 (0x1u << 24) |
| | (SUPC_SR) WKUP Input Status 8
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#define | SUPC_SR_WKUPIS8_DIS (0x0u << 24) |
| | (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS8_EN (0x1u << 24) |
| | (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS9 (0x1u << 25) |
| | (SUPC_SR) WKUP Input Status 9
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#define | SUPC_SR_WKUPIS9_DIS (0x0u << 25) |
| | (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS9_EN (0x1u << 25) |
| | (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS10 (0x1u << 26) |
| | (SUPC_SR) WKUP Input Status 10
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#define | SUPC_SR_WKUPIS10_DIS (0x0u << 26) |
| | (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS10_EN (0x1u << 26) |
| | (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS11 (0x1u << 27) |
| | (SUPC_SR) WKUP Input Status 11
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#define | SUPC_SR_WKUPIS11_DIS (0x0u << 27) |
| | (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS11_EN (0x1u << 27) |
| | (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS12 (0x1u << 28) |
| | (SUPC_SR) WKUP Input Status 12
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#define | SUPC_SR_WKUPIS12_DIS (0x0u << 28) |
| | (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS12_EN (0x1u << 28) |
| | (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS13 (0x1u << 29) |
| | (SUPC_SR) WKUP Input Status 13
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#define | SUPC_SR_WKUPIS13_DIS (0x0u << 29) |
| | (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS13_EN (0x1u << 29) |
| | (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS14 (0x1u << 30) |
| | (SUPC_SR) WKUP Input Status 14
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#define | SUPC_SR_WKUPIS14_DIS (0x0u << 30) |
| | (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS14_EN (0x1u << 30) |
| | (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS15 (0x1u << 31) |
| | (SUPC_SR) WKUP Input Status 15
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#define | SUPC_SR_WKUPIS15_DIS (0x0u << 31) |
| | (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
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#define | SUPC_SR_WKUPIS15_EN (0x1u << 31) |
| | (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
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1.8.11 
