Robobo
component_twi.h
1 /* ----------------------------------------------------------------------------
2  * SAM Software Package License
3  * ----------------------------------------------------------------------------
4  * Copyright (c) 2012, Atmel Corporation
5  *
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following condition is met:
10  *
11  * - Redistributions of source code must retain the above copyright notice,
12  * this list of conditions and the disclaimer below.
13  *
14  * Atmel's name may not be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
20  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
23  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  * ----------------------------------------------------------------------------
28  */
29 
30 #ifndef _SAM3S8_TWI_COMPONENT_
31 #define _SAM3S8_TWI_COMPONENT_
32 
33 /* ============================================================================= */
35 /* ============================================================================= */
38 
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40 
41 typedef struct {
42  WoReg TWI_CR;
43  RwReg TWI_MMR;
44  RwReg TWI_SMR;
45  RwReg TWI_IADR;
46  RwReg TWI_CWGR;
47  RoReg Reserved1[3];
48  RoReg TWI_SR;
49  WoReg TWI_IER;
50  WoReg TWI_IDR;
51  RoReg TWI_IMR;
52  RoReg TWI_RHR;
53  WoReg TWI_THR;
54  RoReg Reserved2[50];
55  RwReg TWI_RPR;
56  RwReg TWI_RCR;
57  RwReg TWI_TPR;
58  RwReg TWI_TCR;
59  RwReg TWI_RNPR;
60  RwReg TWI_RNCR;
61  RwReg TWI_TNPR;
62  RwReg TWI_TNCR;
63  WoReg TWI_PTCR;
64  RoReg TWI_PTSR;
65 } Twi;
66 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
67 /* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
68 #define TWI_CR_START (0x1u << 0)
69 #define TWI_CR_STOP (0x1u << 1)
70 #define TWI_CR_MSEN (0x1u << 2)
71 #define TWI_CR_MSDIS (0x1u << 3)
72 #define TWI_CR_SVEN (0x1u << 4)
73 #define TWI_CR_SVDIS (0x1u << 5)
74 #define TWI_CR_QUICK (0x1u << 6)
75 #define TWI_CR_SWRST (0x1u << 7)
76 /* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
77 #define TWI_MMR_IADRSZ_Pos 8
78 #define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos)
79 #define TWI_MMR_IADRSZ_NONE (0x0u << 8)
80 #define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8)
81 #define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8)
82 #define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8)
83 #define TWI_MMR_MREAD (0x1u << 12)
84 #define TWI_MMR_DADR_Pos 16
85 #define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos)
86 #define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
87 /* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
88 #define TWI_SMR_SADR_Pos 16
89 #define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos)
90 #define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
91 /* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
92 #define TWI_IADR_IADR_Pos 0
93 #define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos)
94 #define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
95 /* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
96 #define TWI_CWGR_CLDIV_Pos 0
97 #define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos)
98 #define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
99 #define TWI_CWGR_CHDIV_Pos 8
100 #define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos)
101 #define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
102 #define TWI_CWGR_CKDIV_Pos 16
103 #define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos)
104 #define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
105 /* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
106 #define TWI_SR_TXCOMP (0x1u << 0)
107 #define TWI_SR_RXRDY (0x1u << 1)
108 #define TWI_SR_TXRDY (0x1u << 2)
109 #define TWI_SR_SVREAD (0x1u << 3)
110 #define TWI_SR_SVACC (0x1u << 4)
111 #define TWI_SR_GACC (0x1u << 5)
112 #define TWI_SR_OVRE (0x1u << 6)
113 #define TWI_SR_NACK (0x1u << 8)
114 #define TWI_SR_ARBLST (0x1u << 9)
115 #define TWI_SR_SCLWS (0x1u << 10)
116 #define TWI_SR_EOSACC (0x1u << 11)
117 #define TWI_SR_ENDRX (0x1u << 12)
118 #define TWI_SR_ENDTX (0x1u << 13)
119 #define TWI_SR_RXBUFF (0x1u << 14)
120 #define TWI_SR_TXBUFE (0x1u << 15)
121 /* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
122 #define TWI_IER_TXCOMP (0x1u << 0)
123 #define TWI_IER_RXRDY (0x1u << 1)
124 #define TWI_IER_TXRDY (0x1u << 2)
125 #define TWI_IER_SVACC (0x1u << 4)
126 #define TWI_IER_GACC (0x1u << 5)
127 #define TWI_IER_OVRE (0x1u << 6)
128 #define TWI_IER_NACK (0x1u << 8)
129 #define TWI_IER_ARBLST (0x1u << 9)
130 #define TWI_IER_SCL_WS (0x1u << 10)
131 #define TWI_IER_EOSACC (0x1u << 11)
132 #define TWI_IER_ENDRX (0x1u << 12)
133 #define TWI_IER_ENDTX (0x1u << 13)
134 #define TWI_IER_RXBUFF (0x1u << 14)
135 #define TWI_IER_TXBUFE (0x1u << 15)
136 /* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
137 #define TWI_IDR_TXCOMP (0x1u << 0)
138 #define TWI_IDR_RXRDY (0x1u << 1)
139 #define TWI_IDR_TXRDY (0x1u << 2)
140 #define TWI_IDR_SVACC (0x1u << 4)
141 #define TWI_IDR_GACC (0x1u << 5)
142 #define TWI_IDR_OVRE (0x1u << 6)
143 #define TWI_IDR_NACK (0x1u << 8)
144 #define TWI_IDR_ARBLST (0x1u << 9)
145 #define TWI_IDR_SCL_WS (0x1u << 10)
146 #define TWI_IDR_EOSACC (0x1u << 11)
147 #define TWI_IDR_ENDRX (0x1u << 12)
148 #define TWI_IDR_ENDTX (0x1u << 13)
149 #define TWI_IDR_RXBUFF (0x1u << 14)
150 #define TWI_IDR_TXBUFE (0x1u << 15)
151 /* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
152 #define TWI_IMR_TXCOMP (0x1u << 0)
153 #define TWI_IMR_RXRDY (0x1u << 1)
154 #define TWI_IMR_TXRDY (0x1u << 2)
155 #define TWI_IMR_SVACC (0x1u << 4)
156 #define TWI_IMR_GACC (0x1u << 5)
157 #define TWI_IMR_OVRE (0x1u << 6)
158 #define TWI_IMR_NACK (0x1u << 8)
159 #define TWI_IMR_ARBLST (0x1u << 9)
160 #define TWI_IMR_SCL_WS (0x1u << 10)
161 #define TWI_IMR_EOSACC (0x1u << 11)
162 #define TWI_IMR_ENDRX (0x1u << 12)
163 #define TWI_IMR_ENDTX (0x1u << 13)
164 #define TWI_IMR_RXBUFF (0x1u << 14)
165 #define TWI_IMR_TXBUFE (0x1u << 15)
166 /* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
167 #define TWI_RHR_RXDATA_Pos 0
168 #define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos)
169 /* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
170 #define TWI_THR_TXDATA_Pos 0
171 #define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos)
172 #define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
173 /* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
174 #define TWI_RPR_RXPTR_Pos 0
175 #define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos)
176 #define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))
177 /* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
178 #define TWI_RCR_RXCTR_Pos 0
179 #define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos)
180 #define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))
181 /* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
182 #define TWI_TPR_TXPTR_Pos 0
183 #define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos)
184 #define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))
185 /* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
186 #define TWI_TCR_TXCTR_Pos 0
187 #define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos)
188 #define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))
189 /* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
190 #define TWI_RNPR_RXNPTR_Pos 0
191 #define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos)
192 #define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))
193 /* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
194 #define TWI_RNCR_RXNCTR_Pos 0
195 #define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos)
196 #define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))
197 /* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
198 #define TWI_TNPR_TXNPTR_Pos 0
199 #define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos)
200 #define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))
201 /* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
202 #define TWI_TNCR_TXNCTR_Pos 0
203 #define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos)
204 #define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))
205 /* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
206 #define TWI_PTCR_RXTEN (0x1u << 0)
207 #define TWI_PTCR_RXTDIS (0x1u << 1)
208 #define TWI_PTCR_TXTEN (0x1u << 8)
209 #define TWI_PTCR_TXTDIS (0x1u << 9)
210 /* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
211 #define TWI_PTSR_RXTEN (0x1u << 0)
212 #define TWI_PTSR_TXTEN (0x1u << 8)
215 
216 
217 #endif /* _SAM3S8_TWI_COMPONENT_ */
RwReg
volatile uint32_t RwReg
Definition: sam3n00a.h:54
WoReg
volatile uint32_t WoReg
Definition: sam3n00a.h:53
RoReg
volatile const uint32_t RoReg
Definition: sam3n00a.h:49
Twi
Twi hardware registers.
Definition: component_twi.h:41