Twi hardware registers. More...

Public Attributes
WoReg	TWI_CR
	(Twi Offset: 0x00) Control Register

RwReg	TWI_MMR
	(Twi Offset: 0x04) Master Mode Register

RwReg	TWI_SMR
	(Twi Offset: 0x08) Slave Mode Register

RwReg	TWI_IADR
	(Twi Offset: 0x0C) Internal Address Register

RwReg	TWI_CWGR
	(Twi Offset: 0x10) Clock Waveform Generator Register

RoReg	Reserved1 [3]

RoReg	TWI_SR
	(Twi Offset: 0x20) Status Register

WoReg	TWI_IER
	(Twi Offset: 0x24) Interrupt Enable Register

WoReg	TWI_IDR
	(Twi Offset: 0x28) Interrupt Disable Register

RoReg	TWI_IMR
	(Twi Offset: 0x2C) Interrupt Mask Register

RoReg	TWI_RHR
	(Twi Offset: 0x30) Receive Holding Register

WoReg	TWI_THR
	(Twi Offset: 0x34) Transmit Holding Register

RoReg	Reserved2 [50]

RwReg	TWI_RPR
	(Twi Offset: 0x100) Receive Pointer Register

RwReg	TWI_RCR
	(Twi Offset: 0x104) Receive Counter Register

RwReg	TWI_TPR
	(Twi Offset: 0x108) Transmit Pointer Register

RwReg	TWI_TCR
	(Twi Offset: 0x10C) Transmit Counter Register

RwReg	TWI_RNPR
	(Twi Offset: 0x110) Receive Next Pointer Register

RwReg	TWI_RNCR
	(Twi Offset: 0x114) Receive Next Counter Register

RwReg	TWI_TNPR
	(Twi Offset: 0x118) Transmit Next Pointer Register

RwReg	TWI_TNCR
	(Twi Offset: 0x11C) Transmit Next Counter Register

WoReg	TWI_PTCR
	(Twi Offset: 0x120) Transfer Control Register

RoReg	TWI_PTSR
	(Twi Offset: 0x124) Transfer Status Register

Detailed Description

Twi hardware registers.

The documentation for this struct was generated from the following file:

Public Attributes