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#define | TWI_CR_START (0x1u << 0) |
| | (TWI_CR) Send a START Condition
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#define | TWI_CR_STOP (0x1u << 1) |
| | (TWI_CR) Send a STOP Condition
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#define | TWI_CR_MSEN (0x1u << 2) |
| | (TWI_CR) TWI Master Mode Enabled
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#define | TWI_CR_MSDIS (0x1u << 3) |
| | (TWI_CR) TWI Master Mode Disabled
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#define | TWI_CR_SVEN (0x1u << 4) |
| | (TWI_CR) TWI Slave Mode Enabled
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#define | TWI_CR_SVDIS (0x1u << 5) |
| | (TWI_CR) TWI Slave Mode Disabled
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#define | TWI_CR_QUICK (0x1u << 6) |
| | (TWI_CR) SMBUS Quick Command
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#define | TWI_CR_SWRST (0x1u << 7) |
| | (TWI_CR) Software Reset
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#define | TWI_MMR_IADRSZ_Pos 8 |
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#define | TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) |
| | (TWI_MMR) Internal Device Address Size
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#define | TWI_MMR_IADRSZ_NONE (0x0u << 8) |
| | (TWI_MMR) No internal device address
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#define | TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) |
| | (TWI_MMR) One-byte internal device address
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#define | TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) |
| | (TWI_MMR) Two-byte internal device address
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#define | TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) |
| | (TWI_MMR) Three-byte internal device address
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#define | TWI_MMR_MREAD (0x1u << 12) |
| | (TWI_MMR) Master Read Direction
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#define | TWI_MMR_DADR_Pos 16 |
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#define | TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) |
| | (TWI_MMR) Device Address
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#define | TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos))) |
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#define | TWI_SMR_SADR_Pos 16 |
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#define | TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) |
| | (TWI_SMR) Slave Address
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#define | TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos))) |
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#define | TWI_IADR_IADR_Pos 0 |
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#define | TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) |
| | (TWI_IADR) Internal Address
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#define | TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos))) |
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#define | TWI_CWGR_CLDIV_Pos 0 |
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#define | TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) |
| | (TWI_CWGR) Clock Low Divider
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#define | TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos))) |
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#define | TWI_CWGR_CHDIV_Pos 8 |
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#define | TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) |
| | (TWI_CWGR) Clock High Divider
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#define | TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos))) |
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#define | TWI_CWGR_CKDIV_Pos 16 |
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#define | TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) |
| | (TWI_CWGR) Clock Divider
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#define | TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos))) |
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#define | TWI_SR_TXCOMP (0x1u << 0) |
| | (TWI_SR) Transmission Completed (automatically set / reset)
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#define | TWI_SR_RXRDY (0x1u << 1) |
| | (TWI_SR) Receive Holding Register Ready (automatically set / reset)
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#define | TWI_SR_TXRDY (0x1u << 2) |
| | (TWI_SR) Transmit Holding Register Ready (automatically set / reset)
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#define | TWI_SR_SVREAD (0x1u << 3) |
| | (TWI_SR) Slave Read (automatically set / reset)
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#define | TWI_SR_SVACC (0x1u << 4) |
| | (TWI_SR) Slave Access (automatically set / reset)
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#define | TWI_SR_GACC (0x1u << 5) |
| | (TWI_SR) General Call Access (clear on read)
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#define | TWI_SR_OVRE (0x1u << 6) |
| | (TWI_SR) Overrun Error (clear on read)
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#define | TWI_SR_NACK (0x1u << 8) |
| | (TWI_SR) Not Acknowledged (clear on read)
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#define | TWI_SR_ARBLST (0x1u << 9) |
| | (TWI_SR) Arbitration Lost (clear on read)
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#define | TWI_SR_SCLWS (0x1u << 10) |
| | (TWI_SR) Clock Wait State (automatically set / reset)
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#define | TWI_SR_EOSACC (0x1u << 11) |
| | (TWI_SR) End Of Slave Access (clear on read)
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#define | TWI_SR_ENDRX (0x1u << 12) |
| | (TWI_SR) End of RX buffer
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#define | TWI_SR_ENDTX (0x1u << 13) |
| | (TWI_SR) End of TX buffer
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#define | TWI_SR_RXBUFF (0x1u << 14) |
| | (TWI_SR) RX Buffer Full
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#define | TWI_SR_TXBUFE (0x1u << 15) |
| | (TWI_SR) TX Buffer Empty
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#define | TWI_IER_TXCOMP (0x1u << 0) |
| | (TWI_IER) Transmission Completed Interrupt Enable
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#define | TWI_IER_RXRDY (0x1u << 1) |
| | (TWI_IER) Receive Holding Register Ready Interrupt Enable
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#define | TWI_IER_TXRDY (0x1u << 2) |
| | (TWI_IER) Transmit Holding Register Ready Interrupt Enable
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#define | TWI_IER_SVACC (0x1u << 4) |
| | (TWI_IER) Slave Access Interrupt Enable
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#define | TWI_IER_GACC (0x1u << 5) |
| | (TWI_IER) General Call Access Interrupt Enable
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#define | TWI_IER_OVRE (0x1u << 6) |
| | (TWI_IER) Overrun Error Interrupt Enable
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#define | TWI_IER_NACK (0x1u << 8) |
| | (TWI_IER) Not Acknowledge Interrupt Enable
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#define | TWI_IER_ARBLST (0x1u << 9) |
| | (TWI_IER) Arbitration Lost Interrupt Enable
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#define | TWI_IER_SCL_WS (0x1u << 10) |
| | (TWI_IER) Clock Wait State Interrupt Enable
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#define | TWI_IER_EOSACC (0x1u << 11) |
| | (TWI_IER) End Of Slave Access Interrupt Enable
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#define | TWI_IER_ENDRX (0x1u << 12) |
| | (TWI_IER) End of Receive Buffer Interrupt Enable
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#define | TWI_IER_ENDTX (0x1u << 13) |
| | (TWI_IER) End of Transmit Buffer Interrupt Enable
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#define | TWI_IER_RXBUFF (0x1u << 14) |
| | (TWI_IER) Receive Buffer Full Interrupt Enable
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#define | TWI_IER_TXBUFE (0x1u << 15) |
| | (TWI_IER) Transmit Buffer Empty Interrupt Enable
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#define | TWI_IDR_TXCOMP (0x1u << 0) |
| | (TWI_IDR) Transmission Completed Interrupt Disable
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#define | TWI_IDR_RXRDY (0x1u << 1) |
| | (TWI_IDR) Receive Holding Register Ready Interrupt Disable
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#define | TWI_IDR_TXRDY (0x1u << 2) |
| | (TWI_IDR) Transmit Holding Register Ready Interrupt Disable
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#define | TWI_IDR_SVACC (0x1u << 4) |
| | (TWI_IDR) Slave Access Interrupt Disable
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#define | TWI_IDR_GACC (0x1u << 5) |
| | (TWI_IDR) General Call Access Interrupt Disable
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#define | TWI_IDR_OVRE (0x1u << 6) |
| | (TWI_IDR) Overrun Error Interrupt Disable
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#define | TWI_IDR_NACK (0x1u << 8) |
| | (TWI_IDR) Not Acknowledge Interrupt Disable
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#define | TWI_IDR_ARBLST (0x1u << 9) |
| | (TWI_IDR) Arbitration Lost Interrupt Disable
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#define | TWI_IDR_SCL_WS (0x1u << 10) |
| | (TWI_IDR) Clock Wait State Interrupt Disable
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#define | TWI_IDR_EOSACC (0x1u << 11) |
| | (TWI_IDR) End Of Slave Access Interrupt Disable
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#define | TWI_IDR_ENDRX (0x1u << 12) |
| | (TWI_IDR) End of Receive Buffer Interrupt Disable
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#define | TWI_IDR_ENDTX (0x1u << 13) |
| | (TWI_IDR) End of Transmit Buffer Interrupt Disable
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#define | TWI_IDR_RXBUFF (0x1u << 14) |
| | (TWI_IDR) Receive Buffer Full Interrupt Disable
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#define | TWI_IDR_TXBUFE (0x1u << 15) |
| | (TWI_IDR) Transmit Buffer Empty Interrupt Disable
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#define | TWI_IMR_TXCOMP (0x1u << 0) |
| | (TWI_IMR) Transmission Completed Interrupt Mask
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#define | TWI_IMR_RXRDY (0x1u << 1) |
| | (TWI_IMR) Receive Holding Register Ready Interrupt Mask
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#define | TWI_IMR_TXRDY (0x1u << 2) |
| | (TWI_IMR) Transmit Holding Register Ready Interrupt Mask
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#define | TWI_IMR_SVACC (0x1u << 4) |
| | (TWI_IMR) Slave Access Interrupt Mask
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#define | TWI_IMR_GACC (0x1u << 5) |
| | (TWI_IMR) General Call Access Interrupt Mask
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#define | TWI_IMR_OVRE (0x1u << 6) |
| | (TWI_IMR) Overrun Error Interrupt Mask
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#define | TWI_IMR_NACK (0x1u << 8) |
| | (TWI_IMR) Not Acknowledge Interrupt Mask
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#define | TWI_IMR_ARBLST (0x1u << 9) |
| | (TWI_IMR) Arbitration Lost Interrupt Mask
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#define | TWI_IMR_SCL_WS (0x1u << 10) |
| | (TWI_IMR) Clock Wait State Interrupt Mask
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#define | TWI_IMR_EOSACC (0x1u << 11) |
| | (TWI_IMR) End Of Slave Access Interrupt Mask
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#define | TWI_IMR_ENDRX (0x1u << 12) |
| | (TWI_IMR) End of Receive Buffer Interrupt Mask
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#define | TWI_IMR_ENDTX (0x1u << 13) |
| | (TWI_IMR) End of Transmit Buffer Interrupt Mask
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#define | TWI_IMR_RXBUFF (0x1u << 14) |
| | (TWI_IMR) Receive Buffer Full Interrupt Mask
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#define | TWI_IMR_TXBUFE (0x1u << 15) |
| | (TWI_IMR) Transmit Buffer Empty Interrupt Mask
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#define | TWI_RHR_RXDATA_Pos 0 |
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#define | TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) |
| | (TWI_RHR) Master or Slave Receive Holding Data
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#define | TWI_THR_TXDATA_Pos 0 |
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#define | TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) |
| | (TWI_THR) Master or Slave Transmit Holding Data
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#define | TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos))) |
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#define | TWI_RPR_RXPTR_Pos 0 |
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#define | TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) |
| | (TWI_RPR) Receive Pointer Register
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#define | TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos))) |
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#define | TWI_RCR_RXCTR_Pos 0 |
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#define | TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) |
| | (TWI_RCR) Receive Counter Register
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#define | TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos))) |
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#define | TWI_TPR_TXPTR_Pos 0 |
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#define | TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) |
| | (TWI_TPR) Transmit Counter Register
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#define | TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos))) |
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#define | TWI_TCR_TXCTR_Pos 0 |
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#define | TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) |
| | (TWI_TCR) Transmit Counter Register
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#define | TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos))) |
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#define | TWI_RNPR_RXNPTR_Pos 0 |
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#define | TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) |
| | (TWI_RNPR) Receive Next Pointer
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#define | TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos))) |
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#define | TWI_RNCR_RXNCTR_Pos 0 |
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#define | TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) |
| | (TWI_RNCR) Receive Next Counter
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#define | TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos))) |
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#define | TWI_TNPR_TXNPTR_Pos 0 |
| |
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#define | TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) |
| | (TWI_TNPR) Transmit Next Pointer
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#define | TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos))) |
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#define | TWI_TNCR_TXNCTR_Pos 0 |
| |
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#define | TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) |
| | (TWI_TNCR) Transmit Counter Next
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#define | TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos))) |
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#define | TWI_PTCR_RXTEN (0x1u << 0) |
| | (TWI_PTCR) Receiver Transfer Enable
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#define | TWI_PTCR_RXTDIS (0x1u << 1) |
| | (TWI_PTCR) Receiver Transfer Disable
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#define | TWI_PTCR_TXTEN (0x1u << 8) |
| | (TWI_PTCR) Transmitter Transfer Enable
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#define | TWI_PTCR_TXTDIS (0x1u << 9) |
| | (TWI_PTCR) Transmitter Transfer Disable
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#define | TWI_PTSR_RXTEN (0x1u << 0) |
| | (TWI_PTSR) Receiver Transfer Enable
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#define | TWI_PTSR_TXTEN (0x1u << 8) |
| | (TWI_PTSR) Transmitter Transfer Enable
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| |
1.8.11 
