component_uart.h

/* ----------------------------------------------------------------------------
 *         SAM Software Package License
 * ----------------------------------------------------------------------------
 * Copyright (c) 2012, Atmel Corporation
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following condition is met:
 *
 * - Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the disclaimer below.
 *
 * Atmel's name may not be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * ----------------------------------------------------------------------------
 */

#ifndef _SAM3N_UART_COMPONENT_
#define _SAM3N_UART_COMPONENT_

/* ============================================================================= */
/* ============================================================================= */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {
  WoReg UART_CR;       
  RwReg UART_MR;       
  WoReg UART_IER;      
  WoReg UART_IDR;      
  RoReg UART_IMR;      
  RoReg UART_SR;       
  RoReg UART_RHR;      
  WoReg UART_THR;      
  RwReg UART_BRGR;     
  RoReg Reserved1[55];
  RwReg UART_RPR;      
  RwReg UART_RCR;      
  RwReg UART_TPR;      
  RwReg UART_TCR;      
  RwReg UART_RNPR;     
  RwReg UART_RNCR;     
  RwReg UART_TNPR;     
  RwReg UART_TNCR;     
  WoReg UART_PTCR;     
  RoReg UART_PTSR;     
} Uart;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
#define UART_CR_RSTRX (0x1u << 2) 
#define UART_CR_RSTTX (0x1u << 3) 
#define UART_CR_RXEN (0x1u << 4) 
#define UART_CR_RXDIS (0x1u << 5) 
#define UART_CR_TXEN (0x1u << 6) 
#define UART_CR_TXDIS (0x1u << 7) 
#define UART_CR_RSTSTA (0x1u << 8) 
/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
#define UART_MR_PAR_Pos 9
#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) 
#define   UART_MR_PAR_EVEN (0x0u << 9) 
#define   UART_MR_PAR_ODD (0x1u << 9) 
#define   UART_MR_PAR_SPACE (0x2u << 9) 
#define   UART_MR_PAR_MARK (0x3u << 9) 
#define   UART_MR_PAR_NO (0x4u << 9) 
#define UART_MR_CHMODE_Pos 14
#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) 
#define   UART_MR_CHMODE_NORMAL (0x0u << 14) 
#define   UART_MR_CHMODE_AUTOMATIC (0x1u << 14) 
#define   UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) 
#define   UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) 
/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
#define UART_IER_RXRDY (0x1u << 0) 
#define UART_IER_TXRDY (0x1u << 1) 
#define UART_IER_ENDRX (0x1u << 3) 
#define UART_IER_ENDTX (0x1u << 4) 
#define UART_IER_OVRE (0x1u << 5) 
#define UART_IER_FRAME (0x1u << 6) 
#define UART_IER_PARE (0x1u << 7) 
#define UART_IER_TXEMPTY (0x1u << 9) 
#define UART_IER_TXBUFE (0x1u << 11) 
#define UART_IER_RXBUFF (0x1u << 12) 
/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
#define UART_IDR_RXRDY (0x1u << 0) 
#define UART_IDR_TXRDY (0x1u << 1) 
#define UART_IDR_ENDRX (0x1u << 3) 
#define UART_IDR_ENDTX (0x1u << 4) 
#define UART_IDR_OVRE (0x1u << 5) 
#define UART_IDR_FRAME (0x1u << 6) 
#define UART_IDR_PARE (0x1u << 7) 
#define UART_IDR_TXEMPTY (0x1u << 9) 
#define UART_IDR_TXBUFE (0x1u << 11) 
#define UART_IDR_RXBUFF (0x1u << 12) 
/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
#define UART_IMR_RXRDY (0x1u << 0) 
#define UART_IMR_TXRDY (0x1u << 1) 
#define UART_IMR_ENDRX (0x1u << 3) 
#define UART_IMR_ENDTX (0x1u << 4) 
#define UART_IMR_OVRE (0x1u << 5) 
#define UART_IMR_FRAME (0x1u << 6) 
#define UART_IMR_PARE (0x1u << 7) 
#define UART_IMR_TXEMPTY (0x1u << 9) 
#define UART_IMR_TXBUFE (0x1u << 11) 
#define UART_IMR_RXBUFF (0x1u << 12) 
/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
#define UART_SR_RXRDY (0x1u << 0) 
#define UART_SR_TXRDY (0x1u << 1) 
#define UART_SR_ENDRX (0x1u << 3) 
#define UART_SR_ENDTX (0x1u << 4) 
#define UART_SR_OVRE (0x1u << 5) 
#define UART_SR_FRAME (0x1u << 6) 
#define UART_SR_PARE (0x1u << 7) 
#define UART_SR_TXEMPTY (0x1u << 9) 
#define UART_SR_TXBUFE (0x1u << 11) 
#define UART_SR_RXBUFF (0x1u << 12) 
/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
#define UART_RHR_RXCHR_Pos 0
#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) 
/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
#define UART_THR_TXCHR_Pos 0
#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) 
#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
#define UART_BRGR_CD_Pos 0
#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) 
#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
#define UART_RPR_RXPTR_Pos 0
#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) 
#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
#define UART_RCR_RXCTR_Pos 0
#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) 
#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
#define UART_TPR_TXPTR_Pos 0
#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) 
#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
#define UART_TCR_TXCTR_Pos 0
#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) 
#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
#define UART_RNPR_RXNPTR_Pos 0
#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) 
#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
#define UART_RNCR_RXNCTR_Pos 0
#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) 
#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
#define UART_TNPR_TXNPTR_Pos 0
#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) 
#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
#define UART_TNCR_TXNCTR_Pos 0
#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) 
#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
#define UART_PTCR_RXTEN (0x1u << 0) 
#define UART_PTCR_RXTDIS (0x1u << 1) 
#define UART_PTCR_TXTEN (0x1u << 8) 
#define UART_PTCR_TXTDIS (0x1u << 9) 
/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
#define UART_PTSR_RXTEN (0x1u << 0) 
#define UART_PTSR_TXTEN (0x1u << 8) 


#endif /* _SAM3N_UART_COMPONENT_ */