component_hsmci.h

/* ----------------------------------------------------------------------------
 *         SAM Software Package License
 * ----------------------------------------------------------------------------
 * Copyright (c) 2012, Atmel Corporation
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following condition is met:
 *
 * - Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the disclaimer below.
 *
 * Atmel's name may not be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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 * ----------------------------------------------------------------------------
 */

#ifndef _SAM3XA_HSMCI_COMPONENT_
#define _SAM3XA_HSMCI_COMPONENT_

/* ============================================================================= */
/* ============================================================================= */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {
  WoReg HSMCI_CR;        
  RwReg HSMCI_MR;        
  RwReg HSMCI_DTOR;      
  RwReg HSMCI_SDCR;      
  RwReg HSMCI_ARGR;      
  WoReg HSMCI_CMDR;      
  RwReg HSMCI_BLKR;      
  RwReg HSMCI_CSTOR;     
  RoReg HSMCI_RSPR[4];   
  RoReg HSMCI_RDR;       
  WoReg HSMCI_TDR;       
  RoReg Reserved1[2];
  RoReg HSMCI_SR;        
  WoReg HSMCI_IER;       
  WoReg HSMCI_IDR;       
  RoReg HSMCI_IMR;       
  RwReg HSMCI_DMA;       
  RwReg HSMCI_CFG;       
  RoReg Reserved2[35];
  RwReg HSMCI_WPMR;      
  RoReg HSMCI_WPSR;      
  RoReg Reserved3[69];
  RwReg HSMCI_FIFO[256]; 
} Hsmci;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
#define HSMCI_CR_MCIEN (0x1u << 0) 
#define HSMCI_CR_MCIDIS (0x1u << 1) 
#define HSMCI_CR_PWSEN (0x1u << 2) 
#define HSMCI_CR_PWSDIS (0x1u << 3) 
#define HSMCI_CR_SWRST (0x1u << 7) 
/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
#define HSMCI_MR_CLKDIV_Pos 0
#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) 
#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
#define HSMCI_MR_PWSDIV_Pos 8
#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) 
#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
#define HSMCI_MR_RDPROOF (0x1u << 11) 
#define HSMCI_MR_WRPROOF (0x1u << 12) 
#define HSMCI_MR_FBYTE (0x1u << 13) 
#define HSMCI_MR_PADV (0x1u << 14) 
/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
#define HSMCI_DTOR_DTOCYC_Pos 0
#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) 
#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
#define HSMCI_DTOR_DTOMUL_Pos 4
#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) 
#define   HSMCI_DTOR_DTOMUL_1 (0x0u << 4) 
#define   HSMCI_DTOR_DTOMUL_16 (0x1u << 4) 
#define   HSMCI_DTOR_DTOMUL_128 (0x2u << 4) 
#define   HSMCI_DTOR_DTOMUL_256 (0x3u << 4) 
#define   HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) 
#define   HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) 
#define   HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) 
#define   HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) 
/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
#define HSMCI_SDCR_SDCSEL_Pos 0
#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) 
#define   HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) 
#define   HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) 
#define   HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) 
#define   HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) 
#define HSMCI_SDCR_SDCBUS_Pos 6
#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) 
#define   HSMCI_SDCR_SDCBUS_1 (0x0u << 6) 
#define   HSMCI_SDCR_SDCBUS_4 (0x2u << 6) 
#define   HSMCI_SDCR_SDCBUS_8 (0x3u << 6) 
/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
#define HSMCI_ARGR_ARG_Pos 0
#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) 
#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
#define HSMCI_CMDR_CMDNB_Pos 0
#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) 
#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
#define HSMCI_CMDR_RSPTYP_Pos 6
#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) 
#define   HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) 
#define   HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) 
#define   HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) 
#define   HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) 
#define HSMCI_CMDR_SPCMD_Pos 8
#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) 
#define   HSMCI_CMDR_SPCMD_STD (0x0u << 8) 
#define   HSMCI_CMDR_SPCMD_INIT (0x1u << 8) 
#define   HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) 
#define   HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) 
#define   HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) 
#define   HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) 
#define   HSMCI_CMDR_SPCMD_BOR (0x6u << 8) 
#define   HSMCI_CMDR_SPCMD_EBO (0x7u << 8) 
#define HSMCI_CMDR_OPDCMD (0x1u << 11) 
#define   HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) 
#define   HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) 
#define HSMCI_CMDR_MAXLAT (0x1u << 12) 
#define   HSMCI_CMDR_MAXLAT_5 (0x0u << 12) 
#define   HSMCI_CMDR_MAXLAT_64 (0x1u << 12) 
#define HSMCI_CMDR_TRCMD_Pos 16
#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) 
#define   HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) 
#define   HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) 
#define   HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) 
#define HSMCI_CMDR_TRDIR (0x1u << 18) 
#define   HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) 
#define   HSMCI_CMDR_TRDIR_READ (0x1u << 18) 
#define HSMCI_CMDR_TRTYP_Pos 19
#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) 
#define   HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) 
#define   HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) 
#define   HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) 
#define   HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) 
#define   HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) 
#define HSMCI_CMDR_IOSPCMD_Pos 24
#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) 
#define   HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) 
#define   HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) 
#define   HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) 
#define HSMCI_CMDR_ATACS (0x1u << 26) 
#define   HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) 
#define   HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) 
#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) 
/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
#define HSMCI_BLKR_BCNT_Pos 0
#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) 
#define   HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) 
#define   HSMCI_BLKR_BCNT_BYTE (0x4u << 0) 
#define   HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) 
#define HSMCI_BLKR_BLKLEN_Pos 16
#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) 
#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
#define HSMCI_CSTOR_CSTOCYC_Pos 0
#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) 
#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
#define HSMCI_CSTOR_CSTOMUL_Pos 4
#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) 
#define   HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) 
#define   HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) 
#define   HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) 
#define   HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) 
#define   HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) 
#define   HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) 
#define   HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) 
#define   HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) 
/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
#define HSMCI_RSPR_RSP_Pos 0
#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) 
/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
#define HSMCI_RDR_DATA_Pos 0
#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) 
/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
#define HSMCI_TDR_DATA_Pos 0
#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) 
#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
#define HSMCI_SR_CMDRDY (0x1u << 0) 
#define HSMCI_SR_RXRDY (0x1u << 1) 
#define HSMCI_SR_TXRDY (0x1u << 2) 
#define HSMCI_SR_BLKE (0x1u << 3) 
#define HSMCI_SR_DTIP (0x1u << 4) 
#define HSMCI_SR_NOTBUSY (0x1u << 5) 
#define HSMCI_SR_SDIOIRQforSlotA (0x1u << 8) 
#define HSMCI_SR_SDIOIRQforSlotB (0x1u << 9) 
#define HSMCI_SR_SDIOWAIT (0x1u << 12) 
#define HSMCI_SR_CSRCV (0x1u << 13) 
#define HSMCI_SR_RINDE (0x1u << 16) 
#define HSMCI_SR_RDIRE (0x1u << 17) 
#define HSMCI_SR_RCRCE (0x1u << 18) 
#define HSMCI_SR_RENDE (0x1u << 19) 
#define HSMCI_SR_RTOE (0x1u << 20) 
#define HSMCI_SR_DCRCE (0x1u << 21) 
#define HSMCI_SR_DTOE (0x1u << 22) 
#define HSMCI_SR_CSTOE (0x1u << 23) 
#define HSMCI_SR_BLKOVRE (0x1u << 24) 
#define HSMCI_SR_DMADONE (0x1u << 25) 
#define HSMCI_SR_FIFOEMPTY (0x1u << 26) 
#define HSMCI_SR_XFRDONE (0x1u << 27) 
#define HSMCI_SR_ACKRCV (0x1u << 28) 
#define HSMCI_SR_ACKRCVE (0x1u << 29) 
#define HSMCI_SR_OVRE (0x1u << 30) 
#define HSMCI_SR_UNRE (0x1u << 31) 
/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
#define HSMCI_IER_CMDRDY (0x1u << 0) 
#define HSMCI_IER_RXRDY (0x1u << 1) 
#define HSMCI_IER_TXRDY (0x1u << 2) 
#define HSMCI_IER_BLKE (0x1u << 3) 
#define HSMCI_IER_DTIP (0x1u << 4) 
#define HSMCI_IER_NOTBUSY (0x1u << 5) 
#define HSMCI_IER_SDIOIRQforSlotA (0x1u << 8) 
#define HSMCI_IER_SDIOIRQforSlotB (0x1u << 9) 
#define HSMCI_IER_SDIOWAIT (0x1u << 12) 
#define HSMCI_IER_CSRCV (0x1u << 13) 
#define HSMCI_IER_RINDE (0x1u << 16) 
#define HSMCI_IER_RDIRE (0x1u << 17) 
#define HSMCI_IER_RCRCE (0x1u << 18) 
#define HSMCI_IER_RENDE (0x1u << 19) 
#define HSMCI_IER_RTOE (0x1u << 20) 
#define HSMCI_IER_DCRCE (0x1u << 21) 
#define HSMCI_IER_DTOE (0x1u << 22) 
#define HSMCI_IER_CSTOE (0x1u << 23) 
#define HSMCI_IER_BLKOVRE (0x1u << 24) 
#define HSMCI_IER_DMADONE (0x1u << 25) 
#define HSMCI_IER_FIFOEMPTY (0x1u << 26) 
#define HSMCI_IER_XFRDONE (0x1u << 27) 
#define HSMCI_IER_ACKRCV (0x1u << 28) 
#define HSMCI_IER_ACKRCVE (0x1u << 29) 
#define HSMCI_IER_OVRE (0x1u << 30) 
#define HSMCI_IER_UNRE (0x1u << 31) 
/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
#define HSMCI_IDR_CMDRDY (0x1u << 0) 
#define HSMCI_IDR_RXRDY (0x1u << 1) 
#define HSMCI_IDR_TXRDY (0x1u << 2) 
#define HSMCI_IDR_BLKE (0x1u << 3) 
#define HSMCI_IDR_DTIP (0x1u << 4) 
#define HSMCI_IDR_NOTBUSY (0x1u << 5) 
#define HSMCI_IDR_SDIOIRQforSlotA (0x1u << 8) 
#define HSMCI_IDR_SDIOIRQforSlotB (0x1u << 9) 
#define HSMCI_IDR_SDIOWAIT (0x1u << 12) 
#define HSMCI_IDR_CSRCV (0x1u << 13) 
#define HSMCI_IDR_RINDE (0x1u << 16) 
#define HSMCI_IDR_RDIRE (0x1u << 17) 
#define HSMCI_IDR_RCRCE (0x1u << 18) 
#define HSMCI_IDR_RENDE (0x1u << 19) 
#define HSMCI_IDR_RTOE (0x1u << 20) 
#define HSMCI_IDR_DCRCE (0x1u << 21) 
#define HSMCI_IDR_DTOE (0x1u << 22) 
#define HSMCI_IDR_CSTOE (0x1u << 23) 
#define HSMCI_IDR_BLKOVRE (0x1u << 24) 
#define HSMCI_IDR_DMADONE (0x1u << 25) 
#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) 
#define HSMCI_IDR_XFRDONE (0x1u << 27) 
#define HSMCI_IDR_ACKRCV (0x1u << 28) 
#define HSMCI_IDR_ACKRCVE (0x1u << 29) 
#define HSMCI_IDR_OVRE (0x1u << 30) 
#define HSMCI_IDR_UNRE (0x1u << 31) 
/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
#define HSMCI_IMR_CMDRDY (0x1u << 0) 
#define HSMCI_IMR_RXRDY (0x1u << 1) 
#define HSMCI_IMR_TXRDY (0x1u << 2) 
#define HSMCI_IMR_BLKE (0x1u << 3) 
#define HSMCI_IMR_DTIP (0x1u << 4) 
#define HSMCI_IMR_NOTBUSY (0x1u << 5) 
#define HSMCI_IMR_SDIOIRQforSlotA (0x1u << 8) 
#define HSMCI_IMR_SDIOIRQforSlotB (0x1u << 9) 
#define HSMCI_IMR_SDIOWAIT (0x1u << 12) 
#define HSMCI_IMR_CSRCV (0x1u << 13) 
#define HSMCI_IMR_RINDE (0x1u << 16) 
#define HSMCI_IMR_RDIRE (0x1u << 17) 
#define HSMCI_IMR_RCRCE (0x1u << 18) 
#define HSMCI_IMR_RENDE (0x1u << 19) 
#define HSMCI_IMR_RTOE (0x1u << 20) 
#define HSMCI_IMR_DCRCE (0x1u << 21) 
#define HSMCI_IMR_DTOE (0x1u << 22) 
#define HSMCI_IMR_CSTOE (0x1u << 23) 
#define HSMCI_IMR_BLKOVRE (0x1u << 24) 
#define HSMCI_IMR_DMADONE (0x1u << 25) 
#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) 
#define HSMCI_IMR_XFRDONE (0x1u << 27) 
#define HSMCI_IMR_ACKRCV (0x1u << 28) 
#define HSMCI_IMR_ACKRCVE (0x1u << 29) 
#define HSMCI_IMR_OVRE (0x1u << 30) 
#define HSMCI_IMR_UNRE (0x1u << 31) 
/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */
#define HSMCI_DMA_OFFSET_Pos 0
#define HSMCI_DMA_OFFSET_Msk (0x3u << HSMCI_DMA_OFFSET_Pos) 
#define HSMCI_DMA_OFFSET(value) ((HSMCI_DMA_OFFSET_Msk & ((value) << HSMCI_DMA_OFFSET_Pos)))
#define HSMCI_DMA_CHKSIZE (0x1u << 4) 
#define   HSMCI_DMA_CHKSIZE_1 (0x0u << 4) 
#define   HSMCI_DMA_CHKSIZE_4 (0x1u << 4) 
#define HSMCI_DMA_DMAEN (0x1u << 8) 
#define HSMCI_DMA_ROPT (0x1u << 12) 
/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
#define HSMCI_CFG_FIFOMODE (0x1u << 0) 
#define HSMCI_CFG_FERRCTRL (0x1u << 4) 
#define HSMCI_CFG_HSMODE (0x1u << 8) 
#define HSMCI_CFG_LSYNC (0x1u << 12) 
/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
#define HSMCI_WPMR_WP_EN (0x1u << 0) 
#define HSMCI_WPMR_WP_KEY_Pos 8
#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) 
#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))
/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
#define HSMCI_WPSR_WP_VS_Pos 0
#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) 
#define   HSMCI_WPSR_WP_VS_NONE (0x0u << 0) 
#define   HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) 
#define   HSMCI_WPSR_WP_VS_RESET (0x2u << 0) 
#define   HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) 
#define HSMCI_WPSR_WP_VSRC_Pos 8
#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) 
/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */
#define HSMCI_FIFO_DATA_Pos 0
#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) 
#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)))

#endif /* _SAM3XA_HSMCI_COMPONENT_ */