Hsmci hardware registers. More...

#include <component_hsmci.h>

Public Attributes
WoReg	HSMCI_CR
	(Hsmci Offset: 0x00) Control Register

RwReg	HSMCI_MR
	(Hsmci Offset: 0x04) Mode Register

RwReg	HSMCI_DTOR
	(Hsmci Offset: 0x08) Data Timeout Register

RwReg	HSMCI_SDCR
	(Hsmci Offset: 0x0C) SD/SDIO Card Register

RwReg	HSMCI_ARGR
	(Hsmci Offset: 0x10) Argument Register

WoReg	HSMCI_CMDR
	(Hsmci Offset: 0x14) Command Register

RwReg	HSMCI_BLKR
	(Hsmci Offset: 0x18) Block Register

RwReg	HSMCI_CSTOR
	(Hsmci Offset: 0x1C) Completion Signal Timeout Register

RoReg	HSMCI_RSPR [4]
	(Hsmci Offset: 0x20) Response Register

RoReg	HSMCI_RDR
	(Hsmci Offset: 0x30) Receive Data Register

WoReg	HSMCI_TDR
	(Hsmci Offset: 0x34) Transmit Data Register

RoReg	Reserved1 [2]

RoReg	HSMCI_SR
	(Hsmci Offset: 0x40) Status Register

WoReg	HSMCI_IER
	(Hsmci Offset: 0x44) Interrupt Enable Register

WoReg	HSMCI_IDR
	(Hsmci Offset: 0x48) Interrupt Disable Register

RoReg	HSMCI_IMR
	(Hsmci Offset: 0x4C) Interrupt Mask Register

RoReg	Reserved2 [1]

RwReg	HSMCI_CFG
	(Hsmci Offset: 0x54) Configuration Register

RoReg	Reserved3 [35]

RwReg	HSMCI_WPMR
	(Hsmci Offset: 0xE4) Write Protection Mode Register

RoReg	HSMCI_WPSR
	(Hsmci Offset: 0xE8) Write Protection Status Register

RoReg	Reserved4 [5]

RwReg	HSMCI_RPR
	(Hsmci Offset: 0x100) Receive Pointer Register

RwReg	HSMCI_RCR
	(Hsmci Offset: 0x104) Receive Counter Register

RwReg	HSMCI_TPR
	(Hsmci Offset: 0x108) Transmit Pointer Register

RwReg	HSMCI_TCR
	(Hsmci Offset: 0x10C) Transmit Counter Register

RwReg	HSMCI_RNPR
	(Hsmci Offset: 0x110) Receive Next Pointer Register

RwReg	HSMCI_RNCR
	(Hsmci Offset: 0x114) Receive Next Counter Register

RwReg	HSMCI_TNPR
	(Hsmci Offset: 0x118) Transmit Next Pointer Register

RwReg	HSMCI_TNCR
	(Hsmci Offset: 0x11C) Transmit Next Counter Register

WoReg	HSMCI_PTCR
	(Hsmci Offset: 0x120) Transfer Control Register

RoReg	HSMCI_PTSR
	(Hsmci Offset: 0x124) Transfer Status Register

RoReg	Reserved5 [54]

RwReg	HSMCI_FIFO [256]
	(Hsmci Offset: 0x200) FIFO Memory Aperture0

RwReg	HSMCI_DMA
	(Hsmci Offset: 0x50) DMA Configuration Register

Detailed Description

Hsmci hardware registers.

The documentation for this struct was generated from the following file:

src/CMSIS/Device/ATMEL/sam3s/include/component/component_hsmci.h

Public Attributes

Detailed Description