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Classes | Macros
High Speed MultiMedia Card Interface

Classes

struct  Hsmci
 Hsmci hardware registers. More...
 

Macros

#define HSMCI_CR_MCIEN   (0x1u << 0)
 (HSMCI_CR) Multi-Media Interface Enable
 
#define HSMCI_CR_MCIDIS   (0x1u << 1)
 (HSMCI_CR) Multi-Media Interface Disable
 
#define HSMCI_CR_PWSEN   (0x1u << 2)
 (HSMCI_CR) Power Save Mode Enable
 
#define HSMCI_CR_PWSDIS   (0x1u << 3)
 (HSMCI_CR) Power Save Mode Disable
 
#define HSMCI_CR_SWRST   (0x1u << 7)
 (HSMCI_CR) Software Reset
 
#define HSMCI_MR_CLKDIV_Pos   0
 
#define HSMCI_MR_CLKDIV_Msk   (0xffu << HSMCI_MR_CLKDIV_Pos)
 (HSMCI_MR) Clock Divider
 
#define HSMCI_MR_CLKDIV(value)   ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
 
#define HSMCI_MR_PWSDIV_Pos   8
 
#define HSMCI_MR_PWSDIV_Msk   (0x7u << HSMCI_MR_PWSDIV_Pos)
 (HSMCI_MR) Power Saving Divider
 
#define HSMCI_MR_PWSDIV(value)   ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
 
#define HSMCI_MR_RDPROOF   (0x1u << 11)
 (HSMCI_MR)
 
#define HSMCI_MR_WRPROOF   (0x1u << 12)
 (HSMCI_MR)
 
#define HSMCI_MR_FBYTE   (0x1u << 13)
 (HSMCI_MR) Force Byte Transfer
 
#define HSMCI_MR_PADV   (0x1u << 14)
 (HSMCI_MR) Padding Value
 
#define HSMCI_MR_PDCMODE   (0x1u << 15)
 (HSMCI_MR) PDC-oriented Mode
 
#define HSMCI_DTOR_DTOCYC_Pos   0
 
#define HSMCI_DTOR_DTOCYC_Msk   (0xfu << HSMCI_DTOR_DTOCYC_Pos)
 (HSMCI_DTOR) Data Timeout Cycle Number
 
#define HSMCI_DTOR_DTOCYC(value)   ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
 
#define HSMCI_DTOR_DTOMUL_Pos   4
 
#define HSMCI_DTOR_DTOMUL_Msk   (0x7u << HSMCI_DTOR_DTOMUL_Pos)
 (HSMCI_DTOR) Data Timeout Multiplier
 
#define HSMCI_DTOR_DTOMUL_1   (0x0u << 4)
 (HSMCI_DTOR) DTOCYC
 
#define HSMCI_DTOR_DTOMUL_16   (0x1u << 4)
 (HSMCI_DTOR) DTOCYC x 16
 
#define HSMCI_DTOR_DTOMUL_128   (0x2u << 4)
 (HSMCI_DTOR) DTOCYC x 128
 
#define HSMCI_DTOR_DTOMUL_256   (0x3u << 4)
 (HSMCI_DTOR) DTOCYC x 256
 
#define HSMCI_DTOR_DTOMUL_1024   (0x4u << 4)
 (HSMCI_DTOR) DTOCYC x 1024
 
#define HSMCI_DTOR_DTOMUL_4096   (0x5u << 4)
 (HSMCI_DTOR) DTOCYC x 4096
 
#define HSMCI_DTOR_DTOMUL_65536   (0x6u << 4)
 (HSMCI_DTOR) DTOCYC x 65536
 
#define HSMCI_DTOR_DTOMUL_1048576   (0x7u << 4)
 (HSMCI_DTOR) DTOCYC x 1048576
 
#define HSMCI_SDCR_SDCSEL_Pos   0
 
#define HSMCI_SDCR_SDCSEL_Msk   (0x3u << HSMCI_SDCR_SDCSEL_Pos)
 (HSMCI_SDCR) SDCard/SDIO Slot
 
#define HSMCI_SDCR_SDCSEL_SLOTA   (0x0u << 0)
 (HSMCI_SDCR) Slot A is selected.
 
#define HSMCI_SDCR_SDCSEL_SLOTB   (0x1u << 0)
 (HSMCI_SDCR) -
 
#define HSMCI_SDCR_SDCSEL_SLOTC   (0x2u << 0)
 (HSMCI_SDCR) -
 
#define HSMCI_SDCR_SDCSEL_SLOTD   (0x3u << 0)
 (HSMCI_SDCR) -
 
#define HSMCI_SDCR_SDCBUS_Pos   6
 
#define HSMCI_SDCR_SDCBUS_Msk   (0x3u << HSMCI_SDCR_SDCBUS_Pos)
 (HSMCI_SDCR) SDCard/SDIO Bus Width
 
#define HSMCI_SDCR_SDCBUS_1   (0x0u << 6)
 (HSMCI_SDCR) 1 bit
 
#define HSMCI_SDCR_SDCBUS_4   (0x2u << 6)
 (HSMCI_SDCR) 4 bit
 
#define HSMCI_SDCR_SDCBUS_8   (0x3u << 6)
 (HSMCI_SDCR) 8 bit
 
#define HSMCI_ARGR_ARG_Pos   0
 
#define HSMCI_ARGR_ARG_Msk   (0xffffffffu << HSMCI_ARGR_ARG_Pos)
 (HSMCI_ARGR) Command Argument
 
#define HSMCI_ARGR_ARG(value)   ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
 
#define HSMCI_CMDR_CMDNB_Pos   0
 
#define HSMCI_CMDR_CMDNB_Msk   (0x3fu << HSMCI_CMDR_CMDNB_Pos)
 (HSMCI_CMDR) Command Number
 
#define HSMCI_CMDR_CMDNB(value)   ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
 
#define HSMCI_CMDR_RSPTYP_Pos   6
 
#define HSMCI_CMDR_RSPTYP_Msk   (0x3u << HSMCI_CMDR_RSPTYP_Pos)
 (HSMCI_CMDR) Response Type
 
#define HSMCI_CMDR_RSPTYP_NORESP   (0x0u << 6)
 (HSMCI_CMDR) No response.
 
#define HSMCI_CMDR_RSPTYP_48_BIT   (0x1u << 6)
 (HSMCI_CMDR) 48-bit response.
 
#define HSMCI_CMDR_RSPTYP_136_BIT   (0x2u << 6)
 (HSMCI_CMDR) 136-bit response.
 
#define HSMCI_CMDR_RSPTYP_R1B   (0x3u << 6)
 (HSMCI_CMDR) R1b response type
 
#define HSMCI_CMDR_SPCMD_Pos   8
 
#define HSMCI_CMDR_SPCMD_Msk   (0x7u << HSMCI_CMDR_SPCMD_Pos)
 (HSMCI_CMDR) Special Command
 
#define HSMCI_CMDR_SPCMD_STD   (0x0u << 8)
 (HSMCI_CMDR) Not a special CMD.
 
#define HSMCI_CMDR_SPCMD_INIT   (0x1u << 8)
 (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence.
 
#define HSMCI_CMDR_SPCMD_SYNC   (0x2u << 8)
 (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command.
 
#define HSMCI_CMDR_SPCMD_CE_ATA   (0x3u << 8)
 (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line.
 
#define HSMCI_CMDR_SPCMD_IT_CMD   (0x4u << 8)
 (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40).
 
#define HSMCI_CMDR_SPCMD_IT_RESP   (0x5u << 8)
 (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40).
 
#define HSMCI_CMDR_SPCMD_BOR   (0x6u << 8)
 (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly.
 
#define HSMCI_CMDR_SPCMD_EBO   (0x7u << 8)
 (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode.
 
#define HSMCI_CMDR_OPDCMD   (0x1u << 11)
 (HSMCI_CMDR) Open Drain Command
 
#define HSMCI_CMDR_OPDCMD_PUSHPULL   (0x0u << 11)
 (HSMCI_CMDR) Push pull command.
 
#define HSMCI_CMDR_OPDCMD_OPENDRAIN   (0x1u << 11)
 (HSMCI_CMDR) Open drain command.
 
#define HSMCI_CMDR_MAXLAT   (0x1u << 12)
 (HSMCI_CMDR) Max Latency for Command to Response
 
#define HSMCI_CMDR_MAXLAT_5   (0x0u << 12)
 (HSMCI_CMDR) 5-cycle max latency.
 
#define HSMCI_CMDR_MAXLAT_64   (0x1u << 12)
 (HSMCI_CMDR) 64-cycle max latency.
 
#define HSMCI_CMDR_TRCMD_Pos   16
 
#define HSMCI_CMDR_TRCMD_Msk   (0x3u << HSMCI_CMDR_TRCMD_Pos)
 (HSMCI_CMDR) Transfer Command
 
#define HSMCI_CMDR_TRCMD_NO_DATA   (0x0u << 16)
 (HSMCI_CMDR) No data transfer
 
#define HSMCI_CMDR_TRCMD_START_DATA   (0x1u << 16)
 (HSMCI_CMDR) Start data transfer
 
#define HSMCI_CMDR_TRCMD_STOP_DATA   (0x2u << 16)
 (HSMCI_CMDR) Stop data transfer
 
#define HSMCI_CMDR_TRDIR   (0x1u << 18)
 (HSMCI_CMDR) Transfer Direction
 
#define HSMCI_CMDR_TRDIR_WRITE   (0x0u << 18)
 (HSMCI_CMDR) Write.
 
#define HSMCI_CMDR_TRDIR_READ   (0x1u << 18)
 (HSMCI_CMDR) Read.
 
#define HSMCI_CMDR_TRTYP_Pos   19
 
#define HSMCI_CMDR_TRTYP_Msk   (0x7u << HSMCI_CMDR_TRTYP_Pos)
 (HSMCI_CMDR) Transfer Type
 
#define HSMCI_CMDR_TRTYP_SINGLE   (0x0u << 19)
 (HSMCI_CMDR) MMC/SDCard Single Block
 
#define HSMCI_CMDR_TRTYP_MULTIPLE   (0x1u << 19)
 (HSMCI_CMDR) MMC/SDCard Multiple Block
 
#define HSMCI_CMDR_TRTYP_STREAM   (0x2u << 19)
 (HSMCI_CMDR) MMC Stream
 
#define HSMCI_CMDR_TRTYP_BYTE   (0x4u << 19)
 (HSMCI_CMDR) SDIO Byte
 
#define HSMCI_CMDR_TRTYP_BLOCK   (0x5u << 19)
 (HSMCI_CMDR) SDIO Block
 
#define HSMCI_CMDR_IOSPCMD_Pos   24
 
#define HSMCI_CMDR_IOSPCMD_Msk   (0x3u << HSMCI_CMDR_IOSPCMD_Pos)
 (HSMCI_CMDR) SDIO Special Command
 
#define HSMCI_CMDR_IOSPCMD_STD   (0x0u << 24)
 (HSMCI_CMDR) Not an SDIO Special Command
 
#define HSMCI_CMDR_IOSPCMD_SUSPEND   (0x1u << 24)
 (HSMCI_CMDR) SDIO Suspend Command
 
#define HSMCI_CMDR_IOSPCMD_RESUME   (0x2u << 24)
 (HSMCI_CMDR) SDIO Resume Command
 
#define HSMCI_CMDR_ATACS   (0x1u << 26)
 (HSMCI_CMDR) ATA with Command Completion Signal
 
#define HSMCI_CMDR_ATACS_NORMAL   (0x0u << 26)
 (HSMCI_CMDR) Normal operation mode.
 
#define HSMCI_CMDR_ATACS_COMPLETION   (0x1u << 26)
 (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR).
 
#define HSMCI_CMDR_BOOT_ACK   (0x1u << 27)
 (HSMCI_CMDR) Boot Operation Acknowledge.
 
#define HSMCI_BLKR_BCNT_Pos   0
 
#define HSMCI_BLKR_BCNT_Msk   (0xffffu << HSMCI_BLKR_BCNT_Pos)
 (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count
 
#define HSMCI_BLKR_BCNT_MULTIPLE   (0x0u << 0)
 (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer.
 
#define HSMCI_BLKR_BCNT_BYTE   (0x4u << 0)
 (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden.
 
#define HSMCI_BLKR_BCNT_BLOCK   (0x5u << 0)
 (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden.
 
#define HSMCI_BLKR_BLKLEN_Pos   16
 
#define HSMCI_BLKR_BLKLEN_Msk   (0xffffu << HSMCI_BLKR_BLKLEN_Pos)
 (HSMCI_BLKR) Data Block Length
 
#define HSMCI_BLKR_BLKLEN(value)   ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
 
#define HSMCI_CSTOR_CSTOCYC_Pos   0
 
#define HSMCI_CSTOR_CSTOCYC_Msk   (0xfu << HSMCI_CSTOR_CSTOCYC_Pos)
 (HSMCI_CSTOR) Completion Signal Timeout Cycle Number
 
#define HSMCI_CSTOR_CSTOCYC(value)   ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
 
#define HSMCI_CSTOR_CSTOMUL_Pos   4
 
#define HSMCI_CSTOR_CSTOMUL_Msk   (0x7u << HSMCI_CSTOR_CSTOMUL_Pos)
 (HSMCI_CSTOR) Completion Signal Timeout Multiplier
 
#define HSMCI_CSTOR_CSTOMUL_1   (0x0u << 4)
 (HSMCI_CSTOR) CSTOCYC x 1
 
#define HSMCI_CSTOR_CSTOMUL_16   (0x1u << 4)
 (HSMCI_CSTOR) CSTOCYC x 16
 
#define HSMCI_CSTOR_CSTOMUL_128   (0x2u << 4)
 (HSMCI_CSTOR) CSTOCYC x 128
 
#define HSMCI_CSTOR_CSTOMUL_256   (0x3u << 4)
 (HSMCI_CSTOR) CSTOCYC x 256
 
#define HSMCI_CSTOR_CSTOMUL_1024   (0x4u << 4)
 (HSMCI_CSTOR) CSTOCYC x 1024
 
#define HSMCI_CSTOR_CSTOMUL_4096   (0x5u << 4)
 (HSMCI_CSTOR) CSTOCYC x 4096
 
#define HSMCI_CSTOR_CSTOMUL_65536   (0x6u << 4)
 (HSMCI_CSTOR) CSTOCYC x 65536
 
#define HSMCI_CSTOR_CSTOMUL_1048576   (0x7u << 4)
 (HSMCI_CSTOR) CSTOCYC x 1048576
 
#define HSMCI_RSPR_RSP_Pos   0
 
#define HSMCI_RSPR_RSP_Msk   (0xffffffffu << HSMCI_RSPR_RSP_Pos)
 (HSMCI_RSPR[4]) Response
 
#define HSMCI_RDR_DATA_Pos   0
 
#define HSMCI_RDR_DATA_Msk   (0xffffffffu << HSMCI_RDR_DATA_Pos)
 (HSMCI_RDR) Data to Read
 
#define HSMCI_TDR_DATA_Pos   0
 
#define HSMCI_TDR_DATA_Msk   (0xffffffffu << HSMCI_TDR_DATA_Pos)
 (HSMCI_TDR) Data to Write
 
#define HSMCI_TDR_DATA(value)   ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
 
#define HSMCI_SR_CMDRDY   (0x1u << 0)
 (HSMCI_SR) Command Ready
 
#define HSMCI_SR_RXRDY   (0x1u << 1)
 (HSMCI_SR) Receiver Ready
 
#define HSMCI_SR_TXRDY   (0x1u << 2)
 (HSMCI_SR) Transmit Ready
 
#define HSMCI_SR_BLKE   (0x1u << 3)
 (HSMCI_SR) Data Block Ended
 
#define HSMCI_SR_DTIP   (0x1u << 4)
 (HSMCI_SR) Data Transfer in Progress
 
#define HSMCI_SR_NOTBUSY   (0x1u << 5)
 (HSMCI_SR) HSMCI Not Busy
 
#define HSMCI_SR_ENDRX   (0x1u << 6)
 (HSMCI_SR) End of RX Buffer
 
#define HSMCI_SR_ENDTX   (0x1u << 7)
 (HSMCI_SR) End of TX Buffer
 
#define HSMCI_SR_SDIOIRQA   (0x1u << 8)
 (HSMCI_SR) SDIO Interrupt for Slot A
 
#define HSMCI_SR_SDIOWAIT   (0x1u << 12)
 (HSMCI_SR) SDIO Read Wait Operation Status
 
#define HSMCI_SR_CSRCV   (0x1u << 13)
 (HSMCI_SR) CE-ATA Completion Signal Received
 
#define HSMCI_SR_RXBUFF   (0x1u << 14)
 (HSMCI_SR) RX Buffer Full
 
#define HSMCI_SR_TXBUFE   (0x1u << 15)
 (HSMCI_SR) TX Buffer Empty
 
#define HSMCI_SR_RINDE   (0x1u << 16)
 (HSMCI_SR) Response Index Error
 
#define HSMCI_SR_RDIRE   (0x1u << 17)
 (HSMCI_SR) Response Direction Error
 
#define HSMCI_SR_RCRCE   (0x1u << 18)
 (HSMCI_SR) Response CRC Error
 
#define HSMCI_SR_RENDE   (0x1u << 19)
 (HSMCI_SR) Response End Bit Error
 
#define HSMCI_SR_RTOE   (0x1u << 20)
 (HSMCI_SR) Response Time-out Error
 
#define HSMCI_SR_DCRCE   (0x1u << 21)
 (HSMCI_SR) Data CRC Error
 
#define HSMCI_SR_DTOE   (0x1u << 22)
 (HSMCI_SR) Data Time-out Error
 
#define HSMCI_SR_CSTOE   (0x1u << 23)
 (HSMCI_SR) Completion Signal Time-out Error
 
#define HSMCI_SR_FIFOEMPTY   (0x1u << 26)
 (HSMCI_SR) FIFO empty flag
 
#define HSMCI_SR_XFRDONE   (0x1u << 27)
 (HSMCI_SR) Transfer Done flag
 
#define HSMCI_SR_ACKRCV   (0x1u << 28)
 (HSMCI_SR) Boot Operation Acknowledge Received
 
#define HSMCI_SR_ACKRCVE   (0x1u << 29)
 (HSMCI_SR) Boot Operation Acknowledge Error
 
#define HSMCI_SR_OVRE   (0x1u << 30)
 (HSMCI_SR) Overrun
 
#define HSMCI_SR_UNRE   (0x1u << 31)
 (HSMCI_SR) Underrun
 
#define HSMCI_IER_CMDRDY   (0x1u << 0)
 (HSMCI_IER) Command Ready Interrupt Enable
 
#define HSMCI_IER_RXRDY   (0x1u << 1)
 (HSMCI_IER) Receiver Ready Interrupt Enable
 
#define HSMCI_IER_TXRDY   (0x1u << 2)
 (HSMCI_IER) Transmit Ready Interrupt Enable
 
#define HSMCI_IER_BLKE   (0x1u << 3)
 (HSMCI_IER) Data Block Ended Interrupt Enable
 
#define HSMCI_IER_DTIP   (0x1u << 4)
 (HSMCI_IER) Data Transfer in Progress Interrupt Enable
 
#define HSMCI_IER_NOTBUSY   (0x1u << 5)
 (HSMCI_IER) Data Not Busy Interrupt Enable
 
#define HSMCI_IER_ENDRX   (0x1u << 6)
 (HSMCI_IER) End of Receive Buffer Interrupt Enable
 
#define HSMCI_IER_ENDTX   (0x1u << 7)
 (HSMCI_IER) End of Transmit Buffer Interrupt Enable
 
#define HSMCI_IER_SDIOIRQA   (0x1u << 8)
 (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable
 
#define HSMCI_IER_SDIOWAIT   (0x1u << 12)
 (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable
 
#define HSMCI_IER_CSRCV   (0x1u << 13)
 (HSMCI_IER) Completion Signal Received Interrupt Enable
 
#define HSMCI_IER_RXBUFF   (0x1u << 14)
 (HSMCI_IER) Receive Buffer Full Interrupt Enable
 
#define HSMCI_IER_TXBUFE   (0x1u << 15)
 (HSMCI_IER) Transmit Buffer Empty Interrupt Enable
 
#define HSMCI_IER_RINDE   (0x1u << 16)
 (HSMCI_IER) Response Index Error Interrupt Enable
 
#define HSMCI_IER_RDIRE   (0x1u << 17)
 (HSMCI_IER) Response Direction Error Interrupt Enable
 
#define HSMCI_IER_RCRCE   (0x1u << 18)
 (HSMCI_IER) Response CRC Error Interrupt Enable
 
#define HSMCI_IER_RENDE   (0x1u << 19)
 (HSMCI_IER) Response End Bit Error Interrupt Enable
 
#define HSMCI_IER_RTOE   (0x1u << 20)
 (HSMCI_IER) Response Time-out Error Interrupt Enable
 
#define HSMCI_IER_DCRCE   (0x1u << 21)
 (HSMCI_IER) Data CRC Error Interrupt Enable
 
#define HSMCI_IER_DTOE   (0x1u << 22)
 (HSMCI_IER) Data Time-out Error Interrupt Enable
 
#define HSMCI_IER_CSTOE   (0x1u << 23)
 (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable
 
#define HSMCI_IER_FIFOEMPTY   (0x1u << 26)
 (HSMCI_IER) FIFO empty Interrupt enable
 
#define HSMCI_IER_XFRDONE   (0x1u << 27)
 (HSMCI_IER) Transfer Done Interrupt enable
 
#define HSMCI_IER_ACKRCV   (0x1u << 28)
 (HSMCI_IER) Boot Acknowledge Interrupt Enable
 
#define HSMCI_IER_ACKRCVE   (0x1u << 29)
 (HSMCI_IER) Boot Acknowledge Error Interrupt Enable
 
#define HSMCI_IER_OVRE   (0x1u << 30)
 (HSMCI_IER) Overrun Interrupt Enable
 
#define HSMCI_IER_UNRE   (0x1u << 31)
 (HSMCI_IER) Underrun Interrupt Enable
 
#define HSMCI_IDR_CMDRDY   (0x1u << 0)
 (HSMCI_IDR) Command Ready Interrupt Disable
 
#define HSMCI_IDR_RXRDY   (0x1u << 1)
 (HSMCI_IDR) Receiver Ready Interrupt Disable
 
#define HSMCI_IDR_TXRDY   (0x1u << 2)
 (HSMCI_IDR) Transmit Ready Interrupt Disable
 
#define HSMCI_IDR_BLKE   (0x1u << 3)
 (HSMCI_IDR) Data Block Ended Interrupt Disable
 
#define HSMCI_IDR_DTIP   (0x1u << 4)
 (HSMCI_IDR) Data Transfer in Progress Interrupt Disable
 
#define HSMCI_IDR_NOTBUSY   (0x1u << 5)
 (HSMCI_IDR) Data Not Busy Interrupt Disable
 
#define HSMCI_IDR_ENDRX   (0x1u << 6)
 (HSMCI_IDR) End of Receive Buffer Interrupt Disable
 
#define HSMCI_IDR_ENDTX   (0x1u << 7)
 (HSMCI_IDR) End of Transmit Buffer Interrupt Disable
 
#define HSMCI_IDR_SDIOIRQA   (0x1u << 8)
 (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable
 
#define HSMCI_IDR_SDIOWAIT   (0x1u << 12)
 (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable
 
#define HSMCI_IDR_CSRCV   (0x1u << 13)
 (HSMCI_IDR) Completion Signal received interrupt Disable
 
#define HSMCI_IDR_RXBUFF   (0x1u << 14)
 (HSMCI_IDR) Receive Buffer Full Interrupt Disable
 
#define HSMCI_IDR_TXBUFE   (0x1u << 15)
 (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable
 
#define HSMCI_IDR_RINDE   (0x1u << 16)
 (HSMCI_IDR) Response Index Error Interrupt Disable
 
#define HSMCI_IDR_RDIRE   (0x1u << 17)
 (HSMCI_IDR) Response Direction Error Interrupt Disable
 
#define HSMCI_IDR_RCRCE   (0x1u << 18)
 (HSMCI_IDR) Response CRC Error Interrupt Disable
 
#define HSMCI_IDR_RENDE   (0x1u << 19)
 (HSMCI_IDR) Response End Bit Error Interrupt Disable
 
#define HSMCI_IDR_RTOE   (0x1u << 20)
 (HSMCI_IDR) Response Time-out Error Interrupt Disable
 
#define HSMCI_IDR_DCRCE   (0x1u << 21)
 (HSMCI_IDR) Data CRC Error Interrupt Disable
 
#define HSMCI_IDR_DTOE   (0x1u << 22)
 (HSMCI_IDR) Data Time-out Error Interrupt Disable
 
#define HSMCI_IDR_CSTOE   (0x1u << 23)
 (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable
 
#define HSMCI_IDR_FIFOEMPTY   (0x1u << 26)
 (HSMCI_IDR) FIFO empty Interrupt Disable
 
#define HSMCI_IDR_XFRDONE   (0x1u << 27)
 (HSMCI_IDR) Transfer Done Interrupt Disable
 
#define HSMCI_IDR_ACKRCV   (0x1u << 28)
 (HSMCI_IDR) Boot Acknowledge Interrupt Disable
 
#define HSMCI_IDR_ACKRCVE   (0x1u << 29)
 (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable
 
#define HSMCI_IDR_OVRE   (0x1u << 30)
 (HSMCI_IDR) Overrun Interrupt Disable
 
#define HSMCI_IDR_UNRE   (0x1u << 31)
 (HSMCI_IDR) Underrun Interrupt Disable
 
#define HSMCI_IMR_CMDRDY   (0x1u << 0)
 (HSMCI_IMR) Command Ready Interrupt Mask
 
#define HSMCI_IMR_RXRDY   (0x1u << 1)
 (HSMCI_IMR) Receiver Ready Interrupt Mask
 
#define HSMCI_IMR_TXRDY   (0x1u << 2)
 (HSMCI_IMR) Transmit Ready Interrupt Mask
 
#define HSMCI_IMR_BLKE   (0x1u << 3)
 (HSMCI_IMR) Data Block Ended Interrupt Mask
 
#define HSMCI_IMR_DTIP   (0x1u << 4)
 (HSMCI_IMR) Data Transfer in Progress Interrupt Mask
 
#define HSMCI_IMR_NOTBUSY   (0x1u << 5)
 (HSMCI_IMR) Data Not Busy Interrupt Mask
 
#define HSMCI_IMR_ENDRX   (0x1u << 6)
 (HSMCI_IMR) End of Receive Buffer Interrupt Mask
 
#define HSMCI_IMR_ENDTX   (0x1u << 7)
 (HSMCI_IMR) End of Transmit Buffer Interrupt Mask
 
#define HSMCI_IMR_SDIOIRQA   (0x1u << 8)
 (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask
 
#define HSMCI_IMR_SDIOWAIT   (0x1u << 12)
 (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask
 
#define HSMCI_IMR_CSRCV   (0x1u << 13)
 (HSMCI_IMR) Completion Signal Received Interrupt Mask
 
#define HSMCI_IMR_RXBUFF   (0x1u << 14)
 (HSMCI_IMR) Receive Buffer Full Interrupt Mask
 
#define HSMCI_IMR_TXBUFE   (0x1u << 15)
 (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask
 
#define HSMCI_IMR_RINDE   (0x1u << 16)
 (HSMCI_IMR) Response Index Error Interrupt Mask
 
#define HSMCI_IMR_RDIRE   (0x1u << 17)
 (HSMCI_IMR) Response Direction Error Interrupt Mask
 
#define HSMCI_IMR_RCRCE   (0x1u << 18)
 (HSMCI_IMR) Response CRC Error Interrupt Mask
 
#define HSMCI_IMR_RENDE   (0x1u << 19)
 (HSMCI_IMR) Response End Bit Error Interrupt Mask
 
#define HSMCI_IMR_RTOE   (0x1u << 20)
 (HSMCI_IMR) Response Time-out Error Interrupt Mask
 
#define HSMCI_IMR_DCRCE   (0x1u << 21)
 (HSMCI_IMR) Data CRC Error Interrupt Mask
 
#define HSMCI_IMR_DTOE   (0x1u << 22)
 (HSMCI_IMR) Data Time-out Error Interrupt Mask
 
#define HSMCI_IMR_CSTOE   (0x1u << 23)
 (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask
 
#define HSMCI_IMR_FIFOEMPTY   (0x1u << 26)
 (HSMCI_IMR) FIFO Empty Interrupt Mask
 
#define HSMCI_IMR_XFRDONE   (0x1u << 27)
 (HSMCI_IMR) Transfer Done Interrupt Mask
 
#define HSMCI_IMR_ACKRCV   (0x1u << 28)
 (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask
 
#define HSMCI_IMR_ACKRCVE   (0x1u << 29)
 (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask
 
#define HSMCI_IMR_OVRE   (0x1u << 30)
 (HSMCI_IMR) Overrun Interrupt Mask
 
#define HSMCI_IMR_UNRE   (0x1u << 31)
 (HSMCI_IMR) Underrun Interrupt Mask
 
#define HSMCI_CFG_FIFOMODE   (0x1u << 0)
 (HSMCI_CFG) HSMCI Internal FIFO control mode
 
#define HSMCI_CFG_FERRCTRL   (0x1u << 4)
 (HSMCI_CFG) Flow Error flag reset control mode
 
#define HSMCI_CFG_HSMODE   (0x1u << 8)
 (HSMCI_CFG) High Speed Mode
 
#define HSMCI_CFG_LSYNC   (0x1u << 12)
 (HSMCI_CFG) Synchronize on the last block
 
#define HSMCI_WPMR_WP_EN   (0x1u << 0)
 (HSMCI_WPMR) Write Protection Enable
 
#define HSMCI_WPMR_WP_KEY_Pos   8
 
#define HSMCI_WPMR_WP_KEY_Msk   (0xffffffu << HSMCI_WPMR_WP_KEY_Pos)
 (HSMCI_WPMR) Write Protection Key password
 
#define HSMCI_WPMR_WP_KEY(value)   ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))
 
#define HSMCI_WPSR_WP_VS_Pos   0
 
#define HSMCI_WPSR_WP_VS_Msk   (0xfu << HSMCI_WPSR_WP_VS_Pos)
 (HSMCI_WPSR) Write Protection Violation Status
 
#define HSMCI_WPSR_WP_VS_NONE   (0x0u << 0)
 (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR)
 
#define HSMCI_WPSR_WP_VS_WRITE   (0x1u << 0)
 (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.)
 
#define HSMCI_WPSR_WP_VS_RESET   (0x2u << 0)
 (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read).
 
#define HSMCI_WPSR_WP_VS_BOTH   (0x3u << 0)
 (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read.
 
#define HSMCI_WPSR_WP_VSRC_Pos   8
 
#define HSMCI_WPSR_WP_VSRC_Msk   (0xffffu << HSMCI_WPSR_WP_VSRC_Pos)
 (HSMCI_WPSR) Write Protection Violation SouRCe
 
#define HSMCI_RPR_RXPTR_Pos   0
 
#define HSMCI_RPR_RXPTR_Msk   (0xffffffffu << HSMCI_RPR_RXPTR_Pos)
 (HSMCI_RPR) Receive Pointer Register
 
#define HSMCI_RPR_RXPTR(value)   ((HSMCI_RPR_RXPTR_Msk & ((value) << HSMCI_RPR_RXPTR_Pos)))
 
#define HSMCI_RCR_RXCTR_Pos   0
 
#define HSMCI_RCR_RXCTR_Msk   (0xffffu << HSMCI_RCR_RXCTR_Pos)
 (HSMCI_RCR) Receive Counter Register
 
#define HSMCI_RCR_RXCTR(value)   ((HSMCI_RCR_RXCTR_Msk & ((value) << HSMCI_RCR_RXCTR_Pos)))
 
#define HSMCI_TPR_TXPTR_Pos   0
 
#define HSMCI_TPR_TXPTR_Msk   (0xffffffffu << HSMCI_TPR_TXPTR_Pos)
 (HSMCI_TPR) Transmit Counter Register
 
#define HSMCI_TPR_TXPTR(value)   ((HSMCI_TPR_TXPTR_Msk & ((value) << HSMCI_TPR_TXPTR_Pos)))
 
#define HSMCI_TCR_TXCTR_Pos   0
 
#define HSMCI_TCR_TXCTR_Msk   (0xffffu << HSMCI_TCR_TXCTR_Pos)
 (HSMCI_TCR) Transmit Counter Register
 
#define HSMCI_TCR_TXCTR(value)   ((HSMCI_TCR_TXCTR_Msk & ((value) << HSMCI_TCR_TXCTR_Pos)))
 
#define HSMCI_RNPR_RXNPTR_Pos   0
 
#define HSMCI_RNPR_RXNPTR_Msk   (0xffffffffu << HSMCI_RNPR_RXNPTR_Pos)
 (HSMCI_RNPR) Receive Next Pointer
 
#define HSMCI_RNPR_RXNPTR(value)   ((HSMCI_RNPR_RXNPTR_Msk & ((value) << HSMCI_RNPR_RXNPTR_Pos)))
 
#define HSMCI_RNCR_RXNCTR_Pos   0
 
#define HSMCI_RNCR_RXNCTR_Msk   (0xffffu << HSMCI_RNCR_RXNCTR_Pos)
 (HSMCI_RNCR) Receive Next Counter
 
#define HSMCI_RNCR_RXNCTR(value)   ((HSMCI_RNCR_RXNCTR_Msk & ((value) << HSMCI_RNCR_RXNCTR_Pos)))
 
#define HSMCI_TNPR_TXNPTR_Pos   0
 
#define HSMCI_TNPR_TXNPTR_Msk   (0xffffffffu << HSMCI_TNPR_TXNPTR_Pos)
 (HSMCI_TNPR) Transmit Next Pointer
 
#define HSMCI_TNPR_TXNPTR(value)   ((HSMCI_TNPR_TXNPTR_Msk & ((value) << HSMCI_TNPR_TXNPTR_Pos)))
 
#define HSMCI_TNCR_TXNCTR_Pos   0
 
#define HSMCI_TNCR_TXNCTR_Msk   (0xffffu << HSMCI_TNCR_TXNCTR_Pos)
 (HSMCI_TNCR) Transmit Counter Next
 
#define HSMCI_TNCR_TXNCTR(value)   ((HSMCI_TNCR_TXNCTR_Msk & ((value) << HSMCI_TNCR_TXNCTR_Pos)))
 
#define HSMCI_PTCR_RXTEN   (0x1u << 0)
 (HSMCI_PTCR) Receiver Transfer Enable
 
#define HSMCI_PTCR_RXTDIS   (0x1u << 1)
 (HSMCI_PTCR) Receiver Transfer Disable
 
#define HSMCI_PTCR_TXTEN   (0x1u << 8)
 (HSMCI_PTCR) Transmitter Transfer Enable
 
#define HSMCI_PTCR_TXTDIS   (0x1u << 9)
 (HSMCI_PTCR) Transmitter Transfer Disable
 
#define HSMCI_PTSR_RXTEN   (0x1u << 0)
 (HSMCI_PTSR) Receiver Transfer Enable
 
#define HSMCI_PTSR_TXTEN   (0x1u << 8)
 (HSMCI_PTSR) Transmitter Transfer Enable
 

Detailed Description

SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface