component_udp.h

/* ----------------------------------------------------------------------------
 *         SAM Software Package License
 * ----------------------------------------------------------------------------
 * Copyright (c) 2012, Atmel Corporation
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following condition is met:
 *
 * - Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the disclaimer below.
 *
 * Atmel's name may not be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * ----------------------------------------------------------------------------
 */

#ifndef _SAM3S_UDP_COMPONENT_
#define _SAM3S_UDP_COMPONENT_

/* ============================================================================= */
/* ============================================================================= */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {
  RoReg UDP_FRM_NUM;  
  RwReg UDP_GLB_STAT; 
  RwReg UDP_FADDR;    
  RoReg Reserved1[1];
  WoReg UDP_IER;      
  WoReg UDP_IDR;      
  RoReg UDP_IMR;      
  RoReg UDP_ISR;      
  WoReg UDP_ICR;      
  RoReg Reserved2[1];
  RwReg UDP_RST_EP;   
  RoReg Reserved3[1];
  RwReg UDP_CSR[8];   
  RwReg UDP_FDR[8];   
  RoReg Reserved4[1];
  RwReg UDP_TXVC;     
} Udp;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */
#define UDP_FRM_NUM_FRM_NUM_Pos 0
#define UDP_FRM_NUM_FRM_NUM_Msk (0x7ffu << UDP_FRM_NUM_FRM_NUM_Pos) 
#define UDP_FRM_NUM_FRM_ERR (0x1u << 16) 
#define UDP_FRM_NUM_FRM_OK (0x1u << 17) 
/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */
#define UDP_GLB_STAT_FADDEN (0x1u << 0) 
#define UDP_GLB_STAT_CONFG (0x1u << 1) 
#define UDP_GLB_STAT_ESR (0x1u << 2) 
#define UDP_GLB_STAT_RSMINPR (0x1u << 3) 
#define UDP_GLB_STAT_RMWUPE (0x1u << 4) 
/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */
#define UDP_FADDR_FADD_Pos 0
#define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) 
#define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos)))
#define UDP_FADDR_FEN (0x1u << 8) 
/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */
#define UDP_IER_EP0INT (0x1u << 0) 
#define UDP_IER_EP1INT (0x1u << 1) 
#define UDP_IER_EP2INT (0x1u << 2) 
#define UDP_IER_EP3INT (0x1u << 3) 
#define UDP_IER_EP4INT (0x1u << 4) 
#define UDP_IER_EP5INT (0x1u << 5) 
#define UDP_IER_EP6INT (0x1u << 6) 
#define UDP_IER_EP7INT (0x1u << 7) 
#define UDP_IER_RXSUSP (0x1u << 8) 
#define UDP_IER_RXRSM (0x1u << 9) 
#define UDP_IER_EXTRSM (0x1u << 10) 
#define UDP_IER_SOFINT (0x1u << 11) 
#define UDP_IER_WAKEUP (0x1u << 13) 
/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */
#define UDP_IDR_EP0INT (0x1u << 0) 
#define UDP_IDR_EP1INT (0x1u << 1) 
#define UDP_IDR_EP2INT (0x1u << 2) 
#define UDP_IDR_EP3INT (0x1u << 3) 
#define UDP_IDR_EP4INT (0x1u << 4) 
#define UDP_IDR_EP5INT (0x1u << 5) 
#define UDP_IDR_EP6INT (0x1u << 6) 
#define UDP_IDR_EP7INT (0x1u << 7) 
#define UDP_IDR_RXSUSP (0x1u << 8) 
#define UDP_IDR_RXRSM (0x1u << 9) 
#define UDP_IDR_EXTRSM (0x1u << 10) 
#define UDP_IDR_SOFINT (0x1u << 11) 
#define UDP_IDR_WAKEUP (0x1u << 13) 
/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */
#define UDP_IMR_EP0INT (0x1u << 0) 
#define UDP_IMR_EP1INT (0x1u << 1) 
#define UDP_IMR_EP2INT (0x1u << 2) 
#define UDP_IMR_EP3INT (0x1u << 3) 
#define UDP_IMR_EP4INT (0x1u << 4) 
#define UDP_IMR_EP5INT (0x1u << 5) 
#define UDP_IMR_EP6INT (0x1u << 6) 
#define UDP_IMR_EP7INT (0x1u << 7) 
#define UDP_IMR_RXSUSP (0x1u << 8) 
#define UDP_IMR_RXRSM (0x1u << 9) 
#define UDP_IMR_EXTRSM (0x1u << 10) 
#define UDP_IMR_SOFINT (0x1u << 11) 
#define UDP_IMR_BIT12 (0x1u << 12) 
#define UDP_IMR_WAKEUP (0x1u << 13) 
/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */
#define UDP_ISR_EP0INT (0x1u << 0) 
#define UDP_ISR_EP1INT (0x1u << 1) 
#define UDP_ISR_EP2INT (0x1u << 2) 
#define UDP_ISR_EP3INT (0x1u << 3) 
#define UDP_ISR_EP4INT (0x1u << 4) 
#define UDP_ISR_EP5INT (0x1u << 5) 
#define UDP_ISR_EP6INT (0x1u << 6) 
#define UDP_ISR_EP7INT (0x1u << 7) 
#define UDP_ISR_RXSUSP (0x1u << 8) 
#define UDP_ISR_RXRSM (0x1u << 9) 
#define UDP_ISR_EXTRSM (0x1u << 10) 
#define UDP_ISR_SOFINT (0x1u << 11) 
#define UDP_ISR_ENDBUSRES (0x1u << 12) 
#define UDP_ISR_WAKEUP (0x1u << 13) 
/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */
#define UDP_ICR_RXSUSP (0x1u << 8) 
#define UDP_ICR_RXRSM (0x1u << 9) 
#define UDP_ICR_EXTRSM (0x1u << 10) 
#define UDP_ICR_SOFINT (0x1u << 11) 
#define UDP_ICR_ENDBUSRES (0x1u << 12) 
#define UDP_ICR_WAKEUP (0x1u << 13) 
/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */
#define UDP_RST_EP_EP0 (0x1u << 0) 
#define UDP_RST_EP_EP1 (0x1u << 1) 
#define UDP_RST_EP_EP2 (0x1u << 2) 
#define UDP_RST_EP_EP3 (0x1u << 3) 
#define UDP_RST_EP_EP4 (0x1u << 4) 
#define UDP_RST_EP_EP5 (0x1u << 5) 
#define UDP_RST_EP_EP6 (0x1u << 6) 
#define UDP_RST_EP_EP7 (0x1u << 7) 
/* -------- UDP_CSR[8] : (UDP Offset: 0x030) Endpoint Control and Status Register -------- */
#define UDP_CSR_TXCOMP (0x1u << 0) 
#define UDP_CSR_RX_DATA_BK0 (0x1u << 1) 
#define UDP_CSR_RXSETUP (0x1u << 2) 
#define UDP_CSR_STALLSENT (0x1u << 3) 
#define UDP_CSR_ISOERROR (0x1u << 3) 
#define UDP_CSR_TXPKTRDY (0x1u << 4) 
#define UDP_CSR_FORCESTALL (0x1u << 5) 
#define UDP_CSR_RX_DATA_BK1 (0x1u << 6) 
#define UDP_CSR_DIR (0x1u << 7) 
#define UDP_CSR_EPTYPE_Pos 8
#define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) 
#define   UDP_CSR_EPTYPE_CTRL (0x0u << 8) 
#define   UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) 
#define   UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) 
#define   UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) 
#define   UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) 
#define   UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) 
#define   UDP_CSR_EPTYPE_INT_IN (0x7u << 8) 
#define UDP_CSR_DTGLE (0x1u << 11) 
#define UDP_CSR_EPEDS (0x1u << 15) 
#define UDP_CSR_RXBYTECNT_Pos 16
#define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) 
#define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos)))
/* -------- UDP_FDR[8] : (UDP Offset: 0x050) Endpoint FIFO Data Register -------- */
#define UDP_FDR_FIFO_DATA_Pos 0
#define UDP_FDR_FIFO_DATA_Msk (0xffu << UDP_FDR_FIFO_DATA_Pos) 
#define UDP_FDR_FIFO_DATA(value) ((UDP_FDR_FIFO_DATA_Msk & ((value) << UDP_FDR_FIFO_DATA_Pos)))
/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */
#define UDP_TXVC_TXVDIS (0x1u << 8) 
#define UDP_TXVC_PUON (0x1u << 9) 


#endif /* _SAM3S_UDP_COMPONENT_ */