component_dmac.h

/* ----------------------------------------------------------------------------
 *         SAM Software Package License
 * ----------------------------------------------------------------------------
 * Copyright (c) 2012, Atmel Corporation
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following condition is met:
 *
 * - Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the disclaimer below.
 *
 * Atmel's name may not be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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 * ----------------------------------------------------------------------------
 */

#ifndef _SAM3U_DMAC_COMPONENT_
#define _SAM3U_DMAC_COMPONENT_

/* ============================================================================= */
/* ============================================================================= */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {
  RwReg       DMAC_SADDR;     
  RwReg       DMAC_DADDR;     
  RwReg       DMAC_DSCR;      
  RwReg       DMAC_CTRLA;     
  RwReg       DMAC_CTRLB;     
  RwReg       DMAC_CFG;       
  RoReg       Reserved1[4];
} DmacCh_num;
#define DMACCH_NUM_NUMBER 4
typedef struct {
  RwReg       DMAC_GCFG;      
  RwReg       DMAC_EN;        
  RwReg       DMAC_SREQ;      
  RwReg       DMAC_CREQ;      
  RwReg       DMAC_LAST;      
  RoReg       Reserved1[1];
  WoReg       DMAC_EBCIER;    
  WoReg       DMAC_EBCIDR;    
  RoReg       DMAC_EBCIMR;    
  RoReg       DMAC_EBCISR;    
  WoReg       DMAC_CHER;      
  WoReg       DMAC_CHDR;      
  RoReg       DMAC_CHSR;      
  RoReg       Reserved2[2];
  DmacCh_num  DMAC_CH_NUM[DMACCH_NUM_NUMBER]; 
  RoReg       Reserved3[66];
  RwReg       DMAC_WPMR;      
  RoReg       DMAC_WPSR;      
} Dmac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */
#define DMAC_GCFG_ARB_CFG (0x1u << 4) 
#define   DMAC_GCFG_ARB_CFG_FIXED (0x0u << 4) 
#define   DMAC_GCFG_ARB_CFG_ROUND_ROBIN (0x1u << 4) 
/* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */
#define DMAC_EN_ENABLE (0x1u << 0) 
/* -------- DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register -------- */
#define DMAC_SREQ_SSREQ0 (0x1u << 0) 
#define DMAC_SREQ_DSREQ0 (0x1u << 1) 
#define DMAC_SREQ_SSREQ1 (0x1u << 2) 
#define DMAC_SREQ_DSREQ1 (0x1u << 3) 
#define DMAC_SREQ_SSREQ2 (0x1u << 4) 
#define DMAC_SREQ_DSREQ2 (0x1u << 5) 
#define DMAC_SREQ_SSREQ3 (0x1u << 6) 
#define DMAC_SREQ_DSREQ3 (0x1u << 7) 
/* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */
#define DMAC_CREQ_SCREQ0 (0x1u << 0) 
#define DMAC_CREQ_DCREQ0 (0x1u << 1) 
#define DMAC_CREQ_SCREQ1 (0x1u << 2) 
#define DMAC_CREQ_DCREQ1 (0x1u << 3) 
#define DMAC_CREQ_SCREQ2 (0x1u << 4) 
#define DMAC_CREQ_DCREQ2 (0x1u << 5) 
#define DMAC_CREQ_SCREQ3 (0x1u << 6) 
#define DMAC_CREQ_DCREQ3 (0x1u << 7) 
/* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */
#define DMAC_LAST_SLAST0 (0x1u << 0) 
#define DMAC_LAST_DLAST0 (0x1u << 1) 
#define DMAC_LAST_SLAST1 (0x1u << 2) 
#define DMAC_LAST_DLAST1 (0x1u << 3) 
#define DMAC_LAST_SLAST2 (0x1u << 4) 
#define DMAC_LAST_DLAST2 (0x1u << 5) 
#define DMAC_LAST_SLAST3 (0x1u << 6) 
#define DMAC_LAST_DLAST3 (0x1u << 7) 
/* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. -------- */
#define DMAC_EBCIER_BTC0 (0x1u << 0) 
#define DMAC_EBCIER_BTC1 (0x1u << 1) 
#define DMAC_EBCIER_BTC2 (0x1u << 2) 
#define DMAC_EBCIER_BTC3 (0x1u << 3) 
#define DMAC_EBCIER_CBTC0 (0x1u << 8) 
#define DMAC_EBCIER_CBTC1 (0x1u << 9) 
#define DMAC_EBCIER_CBTC2 (0x1u << 10) 
#define DMAC_EBCIER_CBTC3 (0x1u << 11) 
#define DMAC_EBCIER_ERR0 (0x1u << 16) 
#define DMAC_EBCIER_ERR1 (0x1u << 17) 
#define DMAC_EBCIER_ERR2 (0x1u << 18) 
#define DMAC_EBCIER_ERR3 (0x1u << 19) 
/* -------- DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. -------- */
#define DMAC_EBCIDR_BTC0 (0x1u << 0) 
#define DMAC_EBCIDR_BTC1 (0x1u << 1) 
#define DMAC_EBCIDR_BTC2 (0x1u << 2) 
#define DMAC_EBCIDR_BTC3 (0x1u << 3) 
#define DMAC_EBCIDR_CBTC0 (0x1u << 8) 
#define DMAC_EBCIDR_CBTC1 (0x1u << 9) 
#define DMAC_EBCIDR_CBTC2 (0x1u << 10) 
#define DMAC_EBCIDR_CBTC3 (0x1u << 11) 
#define DMAC_EBCIDR_ERR0 (0x1u << 16) 
#define DMAC_EBCIDR_ERR1 (0x1u << 17) 
#define DMAC_EBCIDR_ERR2 (0x1u << 18) 
#define DMAC_EBCIDR_ERR3 (0x1u << 19) 
/* -------- DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. -------- */
#define DMAC_EBCIMR_BTC0 (0x1u << 0) 
#define DMAC_EBCIMR_BTC1 (0x1u << 1) 
#define DMAC_EBCIMR_BTC2 (0x1u << 2) 
#define DMAC_EBCIMR_BTC3 (0x1u << 3) 
#define DMAC_EBCIMR_CBTC0 (0x1u << 8) 
#define DMAC_EBCIMR_CBTC1 (0x1u << 9) 
#define DMAC_EBCIMR_CBTC2 (0x1u << 10) 
#define DMAC_EBCIMR_CBTC3 (0x1u << 11) 
#define DMAC_EBCIMR_ERR0 (0x1u << 16) 
#define DMAC_EBCIMR_ERR1 (0x1u << 17) 
#define DMAC_EBCIMR_ERR2 (0x1u << 18) 
#define DMAC_EBCIMR_ERR3 (0x1u << 19) 
/* -------- DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. -------- */
#define DMAC_EBCISR_BTC0 (0x1u << 0) 
#define DMAC_EBCISR_BTC1 (0x1u << 1) 
#define DMAC_EBCISR_BTC2 (0x1u << 2) 
#define DMAC_EBCISR_BTC3 (0x1u << 3) 
#define DMAC_EBCISR_CBTC0 (0x1u << 8) 
#define DMAC_EBCISR_CBTC1 (0x1u << 9) 
#define DMAC_EBCISR_CBTC2 (0x1u << 10) 
#define DMAC_EBCISR_CBTC3 (0x1u << 11) 
#define DMAC_EBCISR_ERR0 (0x1u << 16) 
#define DMAC_EBCISR_ERR1 (0x1u << 17) 
#define DMAC_EBCISR_ERR2 (0x1u << 18) 
#define DMAC_EBCISR_ERR3 (0x1u << 19) 
/* -------- DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register -------- */
#define DMAC_CHER_ENA0 (0x1u << 0) 
#define DMAC_CHER_ENA1 (0x1u << 1) 
#define DMAC_CHER_ENA2 (0x1u << 2) 
#define DMAC_CHER_ENA3 (0x1u << 3) 
#define DMAC_CHER_SUSP0 (0x1u << 8) 
#define DMAC_CHER_SUSP1 (0x1u << 9) 
#define DMAC_CHER_SUSP2 (0x1u << 10) 
#define DMAC_CHER_SUSP3 (0x1u << 11) 
#define DMAC_CHER_KEEP0 (0x1u << 24) 
#define DMAC_CHER_KEEP1 (0x1u << 25) 
#define DMAC_CHER_KEEP2 (0x1u << 26) 
#define DMAC_CHER_KEEP3 (0x1u << 27) 
/* -------- DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register -------- */
#define DMAC_CHDR_DIS0 (0x1u << 0) 
#define DMAC_CHDR_DIS1 (0x1u << 1) 
#define DMAC_CHDR_DIS2 (0x1u << 2) 
#define DMAC_CHDR_DIS3 (0x1u << 3) 
#define DMAC_CHDR_RES0 (0x1u << 8) 
#define DMAC_CHDR_RES1 (0x1u << 9) 
#define DMAC_CHDR_RES2 (0x1u << 10) 
#define DMAC_CHDR_RES3 (0x1u << 11) 
/* -------- DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register -------- */
#define DMAC_CHSR_ENA0 (0x1u << 0) 
#define DMAC_CHSR_ENA1 (0x1u << 1) 
#define DMAC_CHSR_ENA2 (0x1u << 2) 
#define DMAC_CHSR_ENA3 (0x1u << 3) 
#define DMAC_CHSR_SUSP0 (0x1u << 8) 
#define DMAC_CHSR_SUSP1 (0x1u << 9) 
#define DMAC_CHSR_SUSP2 (0x1u << 10) 
#define DMAC_CHSR_SUSP3 (0x1u << 11) 
#define DMAC_CHSR_EMPT0 (0x1u << 16) 
#define DMAC_CHSR_EMPT1 (0x1u << 17) 
#define DMAC_CHSR_EMPT2 (0x1u << 18) 
#define DMAC_CHSR_EMPT3 (0x1u << 19) 
#define DMAC_CHSR_STAL0 (0x1u << 24) 
#define DMAC_CHSR_STAL1 (0x1u << 25) 
#define DMAC_CHSR_STAL2 (0x1u << 26) 
#define DMAC_CHSR_STAL3 (0x1u << 27) 
/* -------- DMAC_SADDR : (DMAC Offset: N/A) DMAC Channel Source Address Register -------- */
#define DMAC_SADDR_SADDR_Pos 0
#define DMAC_SADDR_SADDR_Msk (0xffffffffu << DMAC_SADDR_SADDR_Pos) 
#define DMAC_SADDR_SADDR(value) ((DMAC_SADDR_SADDR_Msk & ((value) << DMAC_SADDR_SADDR_Pos)))
/* -------- DMAC_DADDR : (DMAC Offset: N/A) DMAC Channel Destination Address Register -------- */
#define DMAC_DADDR_DADDR_Pos 0
#define DMAC_DADDR_DADDR_Msk (0xffffffffu << DMAC_DADDR_DADDR_Pos) 
#define DMAC_DADDR_DADDR(value) ((DMAC_DADDR_DADDR_Msk & ((value) << DMAC_DADDR_DADDR_Pos)))
/* -------- DMAC_DSCR : (DMAC Offset: N/A) DMAC Channel Descriptor Address Register -------- */
#define DMAC_DSCR_DSCR_Pos 2
#define DMAC_DSCR_DSCR_Msk (0x3fffffffu << DMAC_DSCR_DSCR_Pos) 
#define DMAC_DSCR_DSCR(value) ((DMAC_DSCR_DSCR_Msk & ((value) << DMAC_DSCR_DSCR_Pos)))
/* -------- DMAC_CTRLA : (DMAC Offset: N/A) DMAC Channel Control A Register -------- */
#define DMAC_CTRLA_BTSIZE_Pos 0
#define DMAC_CTRLA_BTSIZE_Msk (0xffffu << DMAC_CTRLA_BTSIZE_Pos) 
#define DMAC_CTRLA_BTSIZE(value) ((DMAC_CTRLA_BTSIZE_Msk & ((value) << DMAC_CTRLA_BTSIZE_Pos)))
#define DMAC_CTRLA_SCSIZE_Pos 16
#define DMAC_CTRLA_SCSIZE_Msk (0x7u << DMAC_CTRLA_SCSIZE_Pos) 
#define   DMAC_CTRLA_SCSIZE_CHK_1 (0x0u << 16) 
#define   DMAC_CTRLA_SCSIZE_CHK_4 (0x1u << 16) 
#define   DMAC_CTRLA_SCSIZE_CHK_8 (0x2u << 16) 
#define   DMAC_CTRLA_SCSIZE_CHK_16 (0x3u << 16) 
#define   DMAC_CTRLA_SCSIZE_CHK_32 (0x4u << 16) 
#define   DMAC_CTRLA_SCSIZE_CHK_64 (0x5u << 16) 
#define   DMAC_CTRLA_SCSIZE_CHK_128 (0x6u << 16) 
#define   DMAC_CTRLA_SCSIZE_CHK_256 (0x7u << 16) 
#define DMAC_CTRLA_DCSIZE_Pos 20
#define DMAC_CTRLA_DCSIZE_Msk (0x7u << DMAC_CTRLA_DCSIZE_Pos) 
#define   DMAC_CTRLA_DCSIZE_CHK_1 (0x0u << 20) 
#define   DMAC_CTRLA_DCSIZE_CHK_4 (0x1u << 20) 
#define   DMAC_CTRLA_DCSIZE_CHK_8 (0x2u << 20) 
#define   DMAC_CTRLA_DCSIZE_CHK_16 (0x3u << 20) 
#define   DMAC_CTRLA_DCSIZE_CHK_32 (0x4u << 20) 
#define   DMAC_CTRLA_DCSIZE_CHK_64 (0x5u << 20) 
#define   DMAC_CTRLA_DCSIZE_CHK_128 (0x6u << 20) 
#define   DMAC_CTRLA_DCSIZE_CHK_256 (0x7u << 20) 
#define DMAC_CTRLA_SRC_WIDTH_Pos 24
#define DMAC_CTRLA_SRC_WIDTH_Msk (0x3u << DMAC_CTRLA_SRC_WIDTH_Pos) 
#define   DMAC_CTRLA_SRC_WIDTH_BYTE (0x0u << 24) 
#define   DMAC_CTRLA_SRC_WIDTH_HALF_WORD (0x1u << 24) 
#define   DMAC_CTRLA_SRC_WIDTH_WORD (0x2u << 24) 
#define DMAC_CTRLA_DST_WIDTH_Pos 28
#define DMAC_CTRLA_DST_WIDTH_Msk (0x3u << DMAC_CTRLA_DST_WIDTH_Pos) 
#define   DMAC_CTRLA_DST_WIDTH_BYTE (0x0u << 28) 
#define   DMAC_CTRLA_DST_WIDTH_HALF_WORD (0x1u << 28) 
#define   DMAC_CTRLA_DST_WIDTH_WORD (0x2u << 28) 
#define DMAC_CTRLA_DONE (0x1u << 31) 
/* -------- DMAC_CTRLB : (DMAC Offset: N/A) DMAC Channel Control B Register -------- */
#define DMAC_CTRLB_SRC_DSCR (0x1u << 16) 
#define   DMAC_CTRLB_SRC_DSCR_FETCH_FROM_MEM (0x0u << 16) 
#define   DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE (0x1u << 16) 
#define DMAC_CTRLB_DST_DSCR (0x1u << 20) 
#define   DMAC_CTRLB_DST_DSCR_FETCH_FROM_MEM (0x0u << 20) 
#define   DMAC_CTRLB_DST_DSCR_FETCH_DISABLE (0x1u << 20) 
#define DMAC_CTRLB_FC_Pos 21
#define DMAC_CTRLB_FC_Msk (0x7u << DMAC_CTRLB_FC_Pos) 
#define   DMAC_CTRLB_FC_MEM2MEM_DMA_FC (0x0u << 21) 
#define   DMAC_CTRLB_FC_MEM2PER_DMA_FC (0x1u << 21) 
#define   DMAC_CTRLB_FC_PER2MEM_DMA_FC (0x2u << 21) 
#define   DMAC_CTRLB_FC_PER2PER_DMA_FC (0x3u << 21) 
#define DMAC_CTRLB_SRC_INCR_Pos 24
#define DMAC_CTRLB_SRC_INCR_Msk (0x3u << DMAC_CTRLB_SRC_INCR_Pos) 
#define   DMAC_CTRLB_SRC_INCR_INCREMENTING (0x0u << 24) 
#define   DMAC_CTRLB_SRC_INCR_DECREMENTING (0x1u << 24) 
#define   DMAC_CTRLB_SRC_INCR_FIXED (0x2u << 24) 
#define DMAC_CTRLB_DST_INCR_Pos 28
#define DMAC_CTRLB_DST_INCR_Msk (0x3u << DMAC_CTRLB_DST_INCR_Pos) 
#define   DMAC_CTRLB_DST_INCR_INCREMENTING (0x0u << 28) 
#define   DMAC_CTRLB_DST_INCR_DECREMENTING (0x1u << 28) 
#define   DMAC_CTRLB_DST_INCR_FIXED (0x2u << 28) 
#define DMAC_CTRLB_IEN (0x1u << 30) 
/* -------- DMAC_CFG : (DMAC Offset: N/A) DMAC Channel Configuration Register -------- */
#define DMAC_CFG_SRC_PER_Pos 0
#define DMAC_CFG_SRC_PER_Msk (0xfu << DMAC_CFG_SRC_PER_Pos) 
#define DMAC_CFG_SRC_PER(value) ((DMAC_CFG_SRC_PER_Msk & ((value) << DMAC_CFG_SRC_PER_Pos)))
#define DMAC_CFG_DST_PER_Pos 4
#define DMAC_CFG_DST_PER_Msk (0xfu << DMAC_CFG_DST_PER_Pos) 
#define DMAC_CFG_DST_PER(value) ((DMAC_CFG_DST_PER_Msk & ((value) << DMAC_CFG_DST_PER_Pos)))
#define DMAC_CFG_SRC_H2SEL (0x1u << 9) 
#define   DMAC_CFG_SRC_H2SEL_SW (0x0u << 9) 
#define   DMAC_CFG_SRC_H2SEL_HW (0x1u << 9) 
#define DMAC_CFG_DST_H2SEL (0x1u << 13) 
#define   DMAC_CFG_DST_H2SEL_SW (0x0u << 13) 
#define   DMAC_CFG_DST_H2SEL_HW (0x1u << 13) 
#define DMAC_CFG_SOD (0x1u << 16) 
#define   DMAC_CFG_SOD_DISABLE (0x0u << 16) 
#define   DMAC_CFG_SOD_ENABLE (0x1u << 16) 
#define DMAC_CFG_LOCK_IF (0x1u << 20) 
#define   DMAC_CFG_LOCK_IF_DISABLE (0x0u << 20) 
#define   DMAC_CFG_LOCK_IF_ENABLE (0x1u << 20) 
#define DMAC_CFG_LOCK_B (0x1u << 21) 
#define   DMAC_CFG_LOCK_B_DISABLE (0x0u << 21) 
#define DMAC_CFG_LOCK_IF_L (0x1u << 22) 
#define   DMAC_CFG_LOCK_IF_L_CHUNK (0x0u << 22) 
#define   DMAC_CFG_LOCK_IF_L_BUFFER (0x1u << 22) 
#define DMAC_CFG_AHB_PROT_Pos 24
#define DMAC_CFG_AHB_PROT_Msk (0x7u << DMAC_CFG_AHB_PROT_Pos) 
#define DMAC_CFG_AHB_PROT(value) ((DMAC_CFG_AHB_PROT_Msk & ((value) << DMAC_CFG_AHB_PROT_Pos)))
#define DMAC_CFG_FIFOCFG_Pos 28
#define DMAC_CFG_FIFOCFG_Msk (0x3u << DMAC_CFG_FIFOCFG_Pos) 
#define   DMAC_CFG_FIFOCFG_ALAP_CFG (0x0u << 28) 
#define   DMAC_CFG_FIFOCFG_HALF_CFG (0x1u << 28) 
#define   DMAC_CFG_FIFOCFG_ASAP_CFG (0x2u << 28) 
/* -------- DMAC_WPMR : (DMAC Offset: 0x1E4) DMAC Write Protect Mode Register -------- */
#define DMAC_WPMR_WPEN (0x1u << 0) 
#define DMAC_WPMR_WPKEY_Pos 8
#define DMAC_WPMR_WPKEY_Msk (0xffffffu << DMAC_WPMR_WPKEY_Pos) 
#define DMAC_WPMR_WPKEY(value) ((DMAC_WPMR_WPKEY_Msk & ((value) << DMAC_WPMR_WPKEY_Pos)))
/* -------- DMAC_WPSR : (DMAC Offset: 0x1E8) DMAC Write Protect Status Register -------- */
#define DMAC_WPSR_WPVS (0x1u << 0) 
#define DMAC_WPSR_WPVSRC_Pos 8
#define DMAC_WPSR_WPVSRC_Msk (0xffffu << DMAC_WPSR_WPVSRC_Pos) 


#endif /* _SAM3U_DMAC_COMPONENT_ */