DMA Controller

Classes
struct	DmacCh_num
	DmacCh_num hardware registers. More...
struct	Dmac

Macros
#define	DMACCH_NUM_NUMBER   4
	Dmac hardware registers.
#define	DMAC_GCFG_ARB_CFG   (0x1u << 4)
	(DMAC_GCFG) Arbiter Configuration
#define	DMAC_GCFG_ARB_CFG_FIXED   (0x0u << 4)
	(DMAC_GCFG) Fixed priority arbiter.
#define	DMAC_GCFG_ARB_CFG_ROUND_ROBIN   (0x1u << 4)
	(DMAC_GCFG) Modified round robin arbiter.
#define	DMAC_EN_ENABLE   (0x1u << 0)
	(DMAC_EN)
#define	DMAC_SREQ_SSREQ0   (0x1u << 0)
	(DMAC_SREQ) Source Request
#define	DMAC_SREQ_DSREQ0   (0x1u << 1)
	(DMAC_SREQ) Destination Request
#define	DMAC_SREQ_SSREQ1   (0x1u << 2)
	(DMAC_SREQ) Source Request
#define	DMAC_SREQ_DSREQ1   (0x1u << 3)
	(DMAC_SREQ) Destination Request
#define	DMAC_SREQ_SSREQ2   (0x1u << 4)
	(DMAC_SREQ) Source Request
#define	DMAC_SREQ_DSREQ2   (0x1u << 5)
	(DMAC_SREQ) Destination Request
#define	DMAC_SREQ_SSREQ3   (0x1u << 6)
	(DMAC_SREQ) Source Request
#define	DMAC_SREQ_DSREQ3   (0x1u << 7)
	(DMAC_SREQ) Destination Request
#define	DMAC_CREQ_SCREQ0   (0x1u << 0)
	(DMAC_CREQ) Source Chunk Request
#define	DMAC_CREQ_DCREQ0   (0x1u << 1)
	(DMAC_CREQ) Destination Chunk Request
#define	DMAC_CREQ_SCREQ1   (0x1u << 2)
	(DMAC_CREQ) Source Chunk Request
#define	DMAC_CREQ_DCREQ1   (0x1u << 3)
	(DMAC_CREQ) Destination Chunk Request
#define	DMAC_CREQ_SCREQ2   (0x1u << 4)
	(DMAC_CREQ) Source Chunk Request
#define	DMAC_CREQ_DCREQ2   (0x1u << 5)
	(DMAC_CREQ) Destination Chunk Request
#define	DMAC_CREQ_SCREQ3   (0x1u << 6)
	(DMAC_CREQ) Source Chunk Request
#define	DMAC_CREQ_DCREQ3   (0x1u << 7)
	(DMAC_CREQ) Destination Chunk Request
#define	DMAC_LAST_SLAST0   (0x1u << 0)
	(DMAC_LAST) Source Last
#define	DMAC_LAST_DLAST0   (0x1u << 1)
	(DMAC_LAST) Destination Last
#define	DMAC_LAST_SLAST1   (0x1u << 2)
	(DMAC_LAST) Source Last
#define	DMAC_LAST_DLAST1   (0x1u << 3)
	(DMAC_LAST) Destination Last
#define	DMAC_LAST_SLAST2   (0x1u << 4)
	(DMAC_LAST) Source Last
#define	DMAC_LAST_DLAST2   (0x1u << 5)
	(DMAC_LAST) Destination Last
#define	DMAC_LAST_SLAST3   (0x1u << 6)
	(DMAC_LAST) Source Last
#define	DMAC_LAST_DLAST3   (0x1u << 7)
	(DMAC_LAST) Destination Last
#define	DMAC_EBCIER_BTC0   (0x1u << 0)
	(DMAC_EBCIER) Buffer Transfer Completed [3:0]
#define	DMAC_EBCIER_BTC1   (0x1u << 1)
	(DMAC_EBCIER) Buffer Transfer Completed [3:0]
#define	DMAC_EBCIER_BTC2   (0x1u << 2)
	(DMAC_EBCIER) Buffer Transfer Completed [3:0]
#define	DMAC_EBCIER_BTC3   (0x1u << 3)
	(DMAC_EBCIER) Buffer Transfer Completed [3:0]
#define	DMAC_EBCIER_CBTC0   (0x1u << 8)
	(DMAC_EBCIER) Chained Buffer Transfer Completed [3:0]
#define	DMAC_EBCIER_CBTC1   (0x1u << 9)
	(DMAC_EBCIER) Chained Buffer Transfer Completed [3:0]
#define	DMAC_EBCIER_CBTC2   (0x1u << 10)
	(DMAC_EBCIER) Chained Buffer Transfer Completed [3:0]
#define	DMAC_EBCIER_CBTC3   (0x1u << 11)
	(DMAC_EBCIER) Chained Buffer Transfer Completed [3:0]
#define	DMAC_EBCIER_ERR0   (0x1u << 16)
	(DMAC_EBCIER) Access Error [3:0]
#define	DMAC_EBCIER_ERR1   (0x1u << 17)
	(DMAC_EBCIER) Access Error [3:0]
#define	DMAC_EBCIER_ERR2   (0x1u << 18)
	(DMAC_EBCIER) Access Error [3:0]
#define	DMAC_EBCIER_ERR3   (0x1u << 19)
	(DMAC_EBCIER) Access Error [3:0]
#define	DMAC_EBCIDR_BTC0   (0x1u << 0)
	(DMAC_EBCIDR) Buffer Transfer Completed [3:0]
#define	DMAC_EBCIDR_BTC1   (0x1u << 1)
	(DMAC_EBCIDR) Buffer Transfer Completed [3:0]
#define	DMAC_EBCIDR_BTC2   (0x1u << 2)
	(DMAC_EBCIDR) Buffer Transfer Completed [3:0]
#define	DMAC_EBCIDR_BTC3   (0x1u << 3)
	(DMAC_EBCIDR) Buffer Transfer Completed [3:0]
#define	DMAC_EBCIDR_CBTC0   (0x1u << 8)
	(DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0]
#define	DMAC_EBCIDR_CBTC1   (0x1u << 9)
	(DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0]
#define	DMAC_EBCIDR_CBTC2   (0x1u << 10)
	(DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0]
#define	DMAC_EBCIDR_CBTC3   (0x1u << 11)
	(DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0]
#define	DMAC_EBCIDR_ERR0   (0x1u << 16)
	(DMAC_EBCIDR) Access Error [3:0]
#define	DMAC_EBCIDR_ERR1   (0x1u << 17)
	(DMAC_EBCIDR) Access Error [3:0]
#define	DMAC_EBCIDR_ERR2   (0x1u << 18)
	(DMAC_EBCIDR) Access Error [3:0]
#define	DMAC_EBCIDR_ERR3   (0x1u << 19)
	(DMAC_EBCIDR) Access Error [3:0]
#define	DMAC_EBCIMR_BTC0   (0x1u << 0)
	(DMAC_EBCIMR) Buffer Transfer Completed [3:0]
#define	DMAC_EBCIMR_BTC1   (0x1u << 1)
	(DMAC_EBCIMR) Buffer Transfer Completed [3:0]
#define	DMAC_EBCIMR_BTC2   (0x1u << 2)
	(DMAC_EBCIMR) Buffer Transfer Completed [3:0]
#define	DMAC_EBCIMR_BTC3   (0x1u << 3)
	(DMAC_EBCIMR) Buffer Transfer Completed [3:0]
#define	DMAC_EBCIMR_CBTC0   (0x1u << 8)
	(DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0]
#define	DMAC_EBCIMR_CBTC1   (0x1u << 9)
	(DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0]
#define	DMAC_EBCIMR_CBTC2   (0x1u << 10)
	(DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0]
#define	DMAC_EBCIMR_CBTC3   (0x1u << 11)
	(DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0]
#define	DMAC_EBCIMR_ERR0   (0x1u << 16)
	(DMAC_EBCIMR) Access Error [3:0]
#define	DMAC_EBCIMR_ERR1   (0x1u << 17)
	(DMAC_EBCIMR) Access Error [3:0]
#define	DMAC_EBCIMR_ERR2   (0x1u << 18)
	(DMAC_EBCIMR) Access Error [3:0]
#define	DMAC_EBCIMR_ERR3   (0x1u << 19)
	(DMAC_EBCIMR) Access Error [3:0]
#define	DMAC_EBCISR_BTC0   (0x1u << 0)
	(DMAC_EBCISR) Buffer Transfer Completed [3:0]
#define	DMAC_EBCISR_BTC1   (0x1u << 1)
	(DMAC_EBCISR) Buffer Transfer Completed [3:0]
#define	DMAC_EBCISR_BTC2   (0x1u << 2)
	(DMAC_EBCISR) Buffer Transfer Completed [3:0]
#define	DMAC_EBCISR_BTC3   (0x1u << 3)
	(DMAC_EBCISR) Buffer Transfer Completed [3:0]
#define	DMAC_EBCISR_CBTC0   (0x1u << 8)
	(DMAC_EBCISR) Chained Buffer Transfer Completed [3:0]
#define	DMAC_EBCISR_CBTC1   (0x1u << 9)
	(DMAC_EBCISR) Chained Buffer Transfer Completed [3:0]
#define	DMAC_EBCISR_CBTC2   (0x1u << 10)
	(DMAC_EBCISR) Chained Buffer Transfer Completed [3:0]
#define	DMAC_EBCISR_CBTC3   (0x1u << 11)
	(DMAC_EBCISR) Chained Buffer Transfer Completed [3:0]
#define	DMAC_EBCISR_ERR0   (0x1u << 16)
	(DMAC_EBCISR) Access Error [3:0]
#define	DMAC_EBCISR_ERR1   (0x1u << 17)
	(DMAC_EBCISR) Access Error [3:0]
#define	DMAC_EBCISR_ERR2   (0x1u << 18)
	(DMAC_EBCISR) Access Error [3:0]
#define	DMAC_EBCISR_ERR3   (0x1u << 19)
	(DMAC_EBCISR) Access Error [3:0]
#define	DMAC_CHER_ENA0   (0x1u << 0)
	(DMAC_CHER) Enable [3:0]
#define	DMAC_CHER_ENA1   (0x1u << 1)
	(DMAC_CHER) Enable [3:0]
#define	DMAC_CHER_ENA2   (0x1u << 2)
	(DMAC_CHER) Enable [3:0]
#define	DMAC_CHER_ENA3   (0x1u << 3)
	(DMAC_CHER) Enable [3:0]
#define	DMAC_CHER_SUSP0   (0x1u << 8)
	(DMAC_CHER) Suspend [3:0]
#define	DMAC_CHER_SUSP1   (0x1u << 9)
	(DMAC_CHER) Suspend [3:0]
#define	DMAC_CHER_SUSP2   (0x1u << 10)
	(DMAC_CHER) Suspend [3:0]
#define	DMAC_CHER_SUSP3   (0x1u << 11)
	(DMAC_CHER) Suspend [3:0]
#define	DMAC_CHER_KEEP0   (0x1u << 24)
	(DMAC_CHER) Keep on [3:0]
#define	DMAC_CHER_KEEP1   (0x1u << 25)
	(DMAC_CHER) Keep on [3:0]
#define	DMAC_CHER_KEEP2   (0x1u << 26)
	(DMAC_CHER) Keep on [3:0]
#define	DMAC_CHER_KEEP3   (0x1u << 27)
	(DMAC_CHER) Keep on [3:0]
#define	DMAC_CHDR_DIS0   (0x1u << 0)
	(DMAC_CHDR) Disable [3:0]
#define	DMAC_CHDR_DIS1   (0x1u << 1)
	(DMAC_CHDR) Disable [3:0]
#define	DMAC_CHDR_DIS2   (0x1u << 2)
	(DMAC_CHDR) Disable [3:0]
#define	DMAC_CHDR_DIS3   (0x1u << 3)
	(DMAC_CHDR) Disable [3:0]
#define	DMAC_CHDR_RES0   (0x1u << 8)
	(DMAC_CHDR) Resume [3:0]
#define	DMAC_CHDR_RES1   (0x1u << 9)
	(DMAC_CHDR) Resume [3:0]
#define	DMAC_CHDR_RES2   (0x1u << 10)
	(DMAC_CHDR) Resume [3:0]
#define	DMAC_CHDR_RES3   (0x1u << 11)
	(DMAC_CHDR) Resume [3:0]
#define	DMAC_CHSR_ENA0   (0x1u << 0)
	(DMAC_CHSR) Enable [3:0]
#define	DMAC_CHSR_ENA1   (0x1u << 1)
	(DMAC_CHSR) Enable [3:0]
#define	DMAC_CHSR_ENA2   (0x1u << 2)
	(DMAC_CHSR) Enable [3:0]
#define	DMAC_CHSR_ENA3   (0x1u << 3)
	(DMAC_CHSR) Enable [3:0]
#define	DMAC_CHSR_SUSP0   (0x1u << 8)
	(DMAC_CHSR) Suspend [3:0]
#define	DMAC_CHSR_SUSP1   (0x1u << 9)
	(DMAC_CHSR) Suspend [3:0]
#define	DMAC_CHSR_SUSP2   (0x1u << 10)
	(DMAC_CHSR) Suspend [3:0]
#define	DMAC_CHSR_SUSP3   (0x1u << 11)
	(DMAC_CHSR) Suspend [3:0]
#define	DMAC_CHSR_EMPT0   (0x1u << 16)
	(DMAC_CHSR) Empty [3:0]
#define	DMAC_CHSR_EMPT1   (0x1u << 17)
	(DMAC_CHSR) Empty [3:0]
#define	DMAC_CHSR_EMPT2   (0x1u << 18)
	(DMAC_CHSR) Empty [3:0]
#define	DMAC_CHSR_EMPT3   (0x1u << 19)
	(DMAC_CHSR) Empty [3:0]
#define	DMAC_CHSR_STAL0   (0x1u << 24)
	(DMAC_CHSR) Stalled [3:0]
#define	DMAC_CHSR_STAL1   (0x1u << 25)
	(DMAC_CHSR) Stalled [3:0]
#define	DMAC_CHSR_STAL2   (0x1u << 26)
	(DMAC_CHSR) Stalled [3:0]
#define	DMAC_CHSR_STAL3   (0x1u << 27)
	(DMAC_CHSR) Stalled [3:0]
#define	DMAC_SADDR_SADDR_Pos   0
#define	DMAC_SADDR_SADDR_Msk   (0xffffffffu << DMAC_SADDR_SADDR_Pos)
	(DMAC_SADDR) Channel x Source Address
#define	DMAC_SADDR_SADDR(value)   ((DMAC_SADDR_SADDR_Msk & ((value) << DMAC_SADDR_SADDR_Pos)))
#define	DMAC_DADDR_DADDR_Pos   0
#define	DMAC_DADDR_DADDR_Msk   (0xffffffffu << DMAC_DADDR_DADDR_Pos)
	(DMAC_DADDR) Channel x Destination Address
#define	DMAC_DADDR_DADDR(value)   ((DMAC_DADDR_DADDR_Msk & ((value) << DMAC_DADDR_DADDR_Pos)))
#define	DMAC_DSCR_DSCR_Pos   2
#define	DMAC_DSCR_DSCR_Msk   (0x3fffffffu << DMAC_DSCR_DSCR_Pos)
	(DMAC_DSCR) Buffer Transfer Descriptor Address
#define	DMAC_DSCR_DSCR(value)   ((DMAC_DSCR_DSCR_Msk & ((value) << DMAC_DSCR_DSCR_Pos)))
#define	DMAC_CTRLA_BTSIZE_Pos   0
#define	DMAC_CTRLA_BTSIZE_Msk   (0xffffu << DMAC_CTRLA_BTSIZE_Pos)
	(DMAC_CTRLA) Buffer Transfer Size
#define	DMAC_CTRLA_BTSIZE(value)   ((DMAC_CTRLA_BTSIZE_Msk & ((value) << DMAC_CTRLA_BTSIZE_Pos)))
#define	DMAC_CTRLA_SCSIZE_Pos   16
#define	DMAC_CTRLA_SCSIZE_Msk   (0x7u << DMAC_CTRLA_SCSIZE_Pos)
	(DMAC_CTRLA) Source Chunk Transfer Size.
#define	DMAC_CTRLA_SCSIZE_CHK_1   (0x0u << 16)
	(DMAC_CTRLA) 1 data transferred
#define	DMAC_CTRLA_SCSIZE_CHK_4   (0x1u << 16)
	(DMAC_CTRLA) 4 data transferred
#define	DMAC_CTRLA_SCSIZE_CHK_8   (0x2u << 16)
	(DMAC_CTRLA) 8 data transferred
#define	DMAC_CTRLA_SCSIZE_CHK_16   (0x3u << 16)
	(DMAC_CTRLA) 16 data transferred
#define	DMAC_CTRLA_SCSIZE_CHK_32   (0x4u << 16)
	(DMAC_CTRLA) 32 data transferred
#define	DMAC_CTRLA_SCSIZE_CHK_64   (0x5u << 16)
	(DMAC_CTRLA) 64 data transferred
#define	DMAC_CTRLA_SCSIZE_CHK_128   (0x6u << 16)
	(DMAC_CTRLA) 128 data transferred
#define	DMAC_CTRLA_SCSIZE_CHK_256   (0x7u << 16)
	(DMAC_CTRLA) 256 data transferred
#define	DMAC_CTRLA_DCSIZE_Pos   20
#define	DMAC_CTRLA_DCSIZE_Msk   (0x7u << DMAC_CTRLA_DCSIZE_Pos)
	(DMAC_CTRLA) Destination Chunk Transfer Size
#define	DMAC_CTRLA_DCSIZE_CHK_1   (0x0u << 20)
	(DMAC_CTRLA) 1 data transferred
#define	DMAC_CTRLA_DCSIZE_CHK_4   (0x1u << 20)
	(DMAC_CTRLA) 4 data transferred
#define	DMAC_CTRLA_DCSIZE_CHK_8   (0x2u << 20)
	(DMAC_CTRLA) 8 data transferred
#define	DMAC_CTRLA_DCSIZE_CHK_16   (0x3u << 20)
	(DMAC_CTRLA) 16 data transferred
#define	DMAC_CTRLA_DCSIZE_CHK_32   (0x4u << 20)
	(DMAC_CTRLA) 32 data transferred
#define	DMAC_CTRLA_DCSIZE_CHK_64   (0x5u << 20)
	(DMAC_CTRLA) 64 data transferred
#define	DMAC_CTRLA_DCSIZE_CHK_128   (0x6u << 20)
	(DMAC_CTRLA) 128 data transferred
#define	DMAC_CTRLA_DCSIZE_CHK_256   (0x7u << 20)
	(DMAC_CTRLA) 256 data transferred
#define	DMAC_CTRLA_SRC_WIDTH_Pos   24
#define	DMAC_CTRLA_SRC_WIDTH_Msk   (0x3u << DMAC_CTRLA_SRC_WIDTH_Pos)
	(DMAC_CTRLA) Transfer Width for the Source
#define	DMAC_CTRLA_SRC_WIDTH_BYTE   (0x0u << 24)
	(DMAC_CTRLA) the transfer size is set to 8-bit width
#define	DMAC_CTRLA_SRC_WIDTH_HALF_WORD   (0x1u << 24)
	(DMAC_CTRLA) the transfer size is set to 16-bit width
#define	DMAC_CTRLA_SRC_WIDTH_WORD   (0x2u << 24)
	(DMAC_CTRLA) the transfer size is set to 32-bit width
#define	DMAC_CTRLA_DST_WIDTH_Pos   28
#define	DMAC_CTRLA_DST_WIDTH_Msk   (0x3u << DMAC_CTRLA_DST_WIDTH_Pos)
	(DMAC_CTRLA) Transfer Width for the Destination
#define	DMAC_CTRLA_DST_WIDTH_BYTE   (0x0u << 28)
	(DMAC_CTRLA) the transfer size is set to 8-bit width
#define	DMAC_CTRLA_DST_WIDTH_HALF_WORD   (0x1u << 28)
	(DMAC_CTRLA) the transfer size is set to 16-bit width
#define	DMAC_CTRLA_DST_WIDTH_WORD   (0x2u << 28)
	(DMAC_CTRLA) the transfer size is set to 32-bit width
#define	DMAC_CTRLA_DONE   (0x1u << 31)
	(DMAC_CTRLA)
#define	DMAC_CTRLB_SRC_DSCR   (0x1u << 16)
	(DMAC_CTRLB) Source Address Descriptor
#define	DMAC_CTRLB_SRC_DSCR_FETCH_FROM_MEM   (0x0u << 16)
	(DMAC_CTRLB) Source address is updated when the descriptor is fetched from the memory.
#define	DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE   (0x1u << 16)
	(DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the source.
#define	DMAC_CTRLB_DST_DSCR   (0x1u << 20)
	(DMAC_CTRLB) Destination Address Descriptor
#define	DMAC_CTRLB_DST_DSCR_FETCH_FROM_MEM   (0x0u << 20)
	(DMAC_CTRLB) Destination address is updated when the descriptor is fetched from the memory.
#define	DMAC_CTRLB_DST_DSCR_FETCH_DISABLE   (0x1u << 20)
	(DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the destination.
#define	DMAC_CTRLB_FC_Pos   21
#define	DMAC_CTRLB_FC_Msk   (0x7u << DMAC_CTRLB_FC_Pos)
	(DMAC_CTRLB) Flow Control
#define	DMAC_CTRLB_FC_MEM2MEM_DMA_FC   (0x0u << 21)
	(DMAC_CTRLB) Memory-to-Memory Transfer DMAC is flow controller
#define	DMAC_CTRLB_FC_MEM2PER_DMA_FC   (0x1u << 21)
	(DMAC_CTRLB) Memory-to-Peripheral Transfer DMAC is flow controller
#define	DMAC_CTRLB_FC_PER2MEM_DMA_FC   (0x2u << 21)
	(DMAC_CTRLB) Peripheral-to-Memory Transfer DMAC is flow controller
#define	DMAC_CTRLB_FC_PER2PER_DMA_FC   (0x3u << 21)
	(DMAC_CTRLB) Peripheral-to-Peripheral Transfer DMAC is flow controller
#define	DMAC_CTRLB_SRC_INCR_Pos   24
#define	DMAC_CTRLB_SRC_INCR_Msk   (0x3u << DMAC_CTRLB_SRC_INCR_Pos)
	(DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Source
#define	DMAC_CTRLB_SRC_INCR_INCREMENTING   (0x0u << 24)
	(DMAC_CTRLB) The source address is incremented
#define	DMAC_CTRLB_SRC_INCR_DECREMENTING   (0x1u << 24)
	(DMAC_CTRLB) The source address is decremented
#define	DMAC_CTRLB_SRC_INCR_FIXED   (0x2u << 24)
	(DMAC_CTRLB) The source address remains unchanged
#define	DMAC_CTRLB_DST_INCR_Pos   28
#define	DMAC_CTRLB_DST_INCR_Msk   (0x3u << DMAC_CTRLB_DST_INCR_Pos)
	(DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Destination
#define	DMAC_CTRLB_DST_INCR_INCREMENTING   (0x0u << 28)
	(DMAC_CTRLB) The destination address is incremented
#define	DMAC_CTRLB_DST_INCR_DECREMENTING   (0x1u << 28)
	(DMAC_CTRLB) The destination address is decremented
#define	DMAC_CTRLB_DST_INCR_FIXED   (0x2u << 28)
	(DMAC_CTRLB) The destination address remains unchanged
#define	DMAC_CTRLB_IEN   (0x1u << 30)
	(DMAC_CTRLB)
#define	DMAC_CFG_SRC_PER_Pos   0
#define	DMAC_CFG_SRC_PER_Msk   (0xfu << DMAC_CFG_SRC_PER_Pos)
	(DMAC_CFG) Source with Peripheral identifier
#define	DMAC_CFG_SRC_PER(value)   ((DMAC_CFG_SRC_PER_Msk & ((value) << DMAC_CFG_SRC_PER_Pos)))
#define	DMAC_CFG_DST_PER_Pos   4
#define	DMAC_CFG_DST_PER_Msk   (0xfu << DMAC_CFG_DST_PER_Pos)
	(DMAC_CFG) Destination with Peripheral identifier
#define	DMAC_CFG_DST_PER(value)   ((DMAC_CFG_DST_PER_Msk & ((value) << DMAC_CFG_DST_PER_Pos)))
#define	DMAC_CFG_SRC_H2SEL   (0x1u << 9)
	(DMAC_CFG) Software or Hardware Selection for the Source
#define	DMAC_CFG_SRC_H2SEL_SW   (0x0u << 9)
	(DMAC_CFG) Software handshaking interface is used to trigger a transfer request.
#define	DMAC_CFG_SRC_H2SEL_HW   (0x1u << 9)
	(DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request.
#define	DMAC_CFG_DST_H2SEL   (0x1u << 13)
	(DMAC_CFG) Software or Hardware Selection for the Destination
#define	DMAC_CFG_DST_H2SEL_SW   (0x0u << 13)
	(DMAC_CFG) Software handshaking interface is used to trigger a transfer request.
#define	DMAC_CFG_DST_H2SEL_HW   (0x1u << 13)
	(DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request.
#define	DMAC_CFG_SOD   (0x1u << 16)
	(DMAC_CFG) Stop On Done
#define	DMAC_CFG_SOD_DISABLE   (0x0u << 16)
	(DMAC_CFG) STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
#define	DMAC_CFG_SOD_ENABLE   (0x1u << 16)
	(DMAC_CFG) STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.
#define	DMAC_CFG_LOCK_IF   (0x1u << 20)
	(DMAC_CFG) Interface Lock
#define	DMAC_CFG_LOCK_IF_DISABLE   (0x0u << 20)
	(DMAC_CFG) Interface Lock capability is disabled
#define	DMAC_CFG_LOCK_IF_ENABLE   (0x1u << 20)
	(DMAC_CFG) Interface Lock capability is enabled
#define	DMAC_CFG_LOCK_B   (0x1u << 21)
	(DMAC_CFG) Bus Lock
#define	DMAC_CFG_LOCK_B_DISABLE   (0x0u << 21)
	(DMAC_CFG) AHB Bus Locking capability is disabled.
#define	DMAC_CFG_LOCK_IF_L   (0x1u << 22)
	(DMAC_CFG) Master Interface Arbiter Lock
#define	DMAC_CFG_LOCK_IF_L_CHUNK   (0x0u << 22)
	(DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a chunk transfer.
#define	DMAC_CFG_LOCK_IF_L_BUFFER   (0x1u << 22)
	(DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a buffer transfer.
#define	DMAC_CFG_AHB_PROT_Pos   24
#define	DMAC_CFG_AHB_PROT_Msk   (0x7u << DMAC_CFG_AHB_PROT_Pos)
	(DMAC_CFG) AHB Protection
#define	DMAC_CFG_AHB_PROT(value)   ((DMAC_CFG_AHB_PROT_Msk & ((value) << DMAC_CFG_AHB_PROT_Pos)))
#define	DMAC_CFG_FIFOCFG_Pos   28
#define	DMAC_CFG_FIFOCFG_Msk   (0x3u << DMAC_CFG_FIFOCFG_Pos)
	(DMAC_CFG) FIFO Configuration
#define	DMAC_CFG_FIFOCFG_ALAP_CFG   (0x0u << 28)
	(DMAC_CFG) The largest defined length AHB burst is performed on the destination AHB interface.
#define	DMAC_CFG_FIFOCFG_HALF_CFG   (0x1u << 28)
	(DMAC_CFG) When half FIFO size is available/filled, a source/destination request is serviced.
#define	DMAC_CFG_FIFOCFG_ASAP_CFG   (0x2u << 28)
	(DMAC_CFG) When there is enough space/data available to perform a single AHB access, then the request is serviced.
#define	DMAC_WPMR_WPEN   (0x1u << 0)
	(DMAC_WPMR) Write Protect Enable
#define	DMAC_WPMR_WPKEY_Pos   8
#define	DMAC_WPMR_WPKEY_Msk   (0xffffffu << DMAC_WPMR_WPKEY_Pos)
	(DMAC_WPMR) Write Protect KEY
#define	DMAC_WPMR_WPKEY(value)   ((DMAC_WPMR_WPKEY_Msk & ((value) << DMAC_WPMR_WPKEY_Pos)))
#define	DMAC_WPSR_WPVS   (0x1u << 0)
	(DMAC_WPSR) Write Protect Violation Status
#define	DMAC_WPSR_WPVSRC_Pos   8
#define	DMAC_WPSR_WPVSRC_Msk   (0xffffu << DMAC_WPSR_WPVSRC_Pos)
	(DMAC_WPSR) Write Protect Violation Source

Detailed Description

SOFTWARE API DEFINITION FOR DMA Controller