component_udphs.h

/* ----------------------------------------------------------------------------
 *         SAM Software Package License
 * ----------------------------------------------------------------------------
 * Copyright (c) 2012, Atmel Corporation
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following condition is met:
 *
 * - Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the disclaimer below.
 *
 * Atmel's name may not be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * ----------------------------------------------------------------------------
 */

#ifndef _SAM3U_UDPHS_COMPONENT_
#define _SAM3U_UDPHS_COMPONENT_

/* ============================================================================= */
/* ============================================================================= */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {
  RwReg     UDPHS_DMANXTDSC;  
  RwReg     UDPHS_DMAADDRESS; 
  RwReg     UDPHS_DMACONTROL; 
  RwReg     UDPHS_DMASTATUS;  
} UdphsDma;
typedef struct {
  RwReg     UDPHS_EPTCFG;     
  RwReg     UDPHS_EPTCTLENB;  
  RwReg     UDPHS_EPTCTLDIS;  
  RwReg     UDPHS_EPTCTL;     
  RoReg     Reserved1[1];
  RwReg     UDPHS_EPTSETSTA;  
  RwReg     UDPHS_EPTCLRSTA;  
  RwReg     UDPHS_EPTSTA;     
} UdphsEpt;
#define UDPHSEPT_NUMBER 7
#define UDPHSDMA_NUMBER 6
typedef struct {
  RwReg     UDPHS_CTRL;       
  RoReg     UDPHS_FNUM;       
  RoReg     Reserved1[2];
  RwReg     UDPHS_IEN;        
  RoReg     UDPHS_INTSTA;     
  WoReg     UDPHS_CLRINT;     
  WoReg     UDPHS_EPTRST;     
  RoReg     Reserved2[48];
  RwReg     UDPHS_TST;        
  RoReg     Reserved3[3];
  RoReg     UDPHS_IPNAME1;    
  RoReg     UDPHS_IPNAME2;    
  RoReg     UDPHS_IPFEATURES; 
  RoReg     Reserved4[1];
  UdphsEpt  UDPHS_EPT[UDPHSEPT_NUMBER]; 
  RoReg     Reserved5[72];
  UdphsDma  UDPHS_DMA[UDPHSDMA_NUMBER]; 
} Udphs;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- UDPHS_CTRL : (UDPHS Offset: 0x00) UDPHS Control Register -------- */
#define UDPHS_CTRL_DEV_ADDR_Pos 0
#define UDPHS_CTRL_DEV_ADDR_Msk (0x7fu << UDPHS_CTRL_DEV_ADDR_Pos) 
#define UDPHS_CTRL_DEV_ADDR(value) ((UDPHS_CTRL_DEV_ADDR_Msk & ((value) << UDPHS_CTRL_DEV_ADDR_Pos)))
#define UDPHS_CTRL_FADDR_EN (0x1u << 7) 
#define UDPHS_CTRL_EN_UDPHS (0x1u << 8) 
#define UDPHS_CTRL_DETACH (0x1u << 9) 
#define UDPHS_CTRL_REWAKEUP (0x1u << 10) 
#define UDPHS_CTRL_PULLD_DIS (0x1u << 11) 
/* -------- UDPHS_FNUM : (UDPHS Offset: 0x04) UDPHS Frame Number Register -------- */
#define UDPHS_FNUM_MICRO_FRAME_NUM_Pos 0
#define UDPHS_FNUM_MICRO_FRAME_NUM_Msk (0x7u << UDPHS_FNUM_MICRO_FRAME_NUM_Pos) 
#define UDPHS_FNUM_FRAME_NUMBER_Pos 3
#define UDPHS_FNUM_FRAME_NUMBER_Msk (0x7ffu << UDPHS_FNUM_FRAME_NUMBER_Pos) 
#define UDPHS_FNUM_FNUM_ERR (0x1u << 31) 
/* -------- UDPHS_IEN : (UDPHS Offset: 0x10) UDPHS Interrupt Enable Register -------- */
#define UDPHS_IEN_DET_SUSPD (0x1u << 1) 
#define UDPHS_IEN_MICRO_SOF (0x1u << 2) 
#define UDPHS_IEN_INT_SOF (0x1u << 3) 
#define UDPHS_IEN_ENDRESET (0x1u << 4) 
#define UDPHS_IEN_WAKE_UP (0x1u << 5) 
#define UDPHS_IEN_ENDOFRSM (0x1u << 6) 
#define UDPHS_IEN_UPSTR_RES (0x1u << 7) 
#define UDPHS_IEN_EPT_0 (0x1u << 8) 
#define UDPHS_IEN_EPT_1 (0x1u << 9) 
#define UDPHS_IEN_EPT_2 (0x1u << 10) 
#define UDPHS_IEN_EPT_3 (0x1u << 11) 
#define UDPHS_IEN_EPT_4 (0x1u << 12) 
#define UDPHS_IEN_EPT_5 (0x1u << 13) 
#define UDPHS_IEN_EPT_6 (0x1u << 14) 
#define UDPHS_IEN_DMA_1 (0x1u << 25) 
#define UDPHS_IEN_DMA_2 (0x1u << 26) 
#define UDPHS_IEN_DMA_3 (0x1u << 27) 
#define UDPHS_IEN_DMA_4 (0x1u << 28) 
#define UDPHS_IEN_DMA_5 (0x1u << 29) 
#define UDPHS_IEN_DMA_6 (0x1u << 30) 
/* -------- UDPHS_INTSTA : (UDPHS Offset: 0x14) UDPHS Interrupt Status Register -------- */
#define UDPHS_INTSTA_SPEED (0x1u << 0) 
#define UDPHS_INTSTA_DET_SUSPD (0x1u << 1) 
#define UDPHS_INTSTA_MICRO_SOF (0x1u << 2) 
#define UDPHS_INTSTA_INT_SOF (0x1u << 3) 
#define UDPHS_INTSTA_ENDRESET (0x1u << 4) 
#define UDPHS_INTSTA_WAKE_UP (0x1u << 5) 
#define UDPHS_INTSTA_ENDOFRSM (0x1u << 6) 
#define UDPHS_INTSTA_UPSTR_RES (0x1u << 7) 
#define UDPHS_INTSTA_EPT_0 (0x1u << 8) 
#define UDPHS_INTSTA_EPT_1 (0x1u << 9) 
#define UDPHS_INTSTA_EPT_2 (0x1u << 10) 
#define UDPHS_INTSTA_EPT_3 (0x1u << 11) 
#define UDPHS_INTSTA_EPT_4 (0x1u << 12) 
#define UDPHS_INTSTA_EPT_5 (0x1u << 13) 
#define UDPHS_INTSTA_EPT_6 (0x1u << 14) 
#define UDPHS_INTSTA_DMA_1 (0x1u << 25) 
#define UDPHS_INTSTA_DMA_2 (0x1u << 26) 
#define UDPHS_INTSTA_DMA_3 (0x1u << 27) 
#define UDPHS_INTSTA_DMA_4 (0x1u << 28) 
#define UDPHS_INTSTA_DMA_5 (0x1u << 29) 
#define UDPHS_INTSTA_DMA_6 (0x1u << 30) 
/* -------- UDPHS_CLRINT : (UDPHS Offset: 0x18) UDPHS Clear Interrupt Register -------- */
#define UDPHS_CLRINT_DET_SUSPD (0x1u << 1) 
#define UDPHS_CLRINT_MICRO_SOF (0x1u << 2) 
#define UDPHS_CLRINT_INT_SOF (0x1u << 3) 
#define UDPHS_CLRINT_ENDRESET (0x1u << 4) 
#define UDPHS_CLRINT_WAKE_UP (0x1u << 5) 
#define UDPHS_CLRINT_ENDOFRSM (0x1u << 6) 
#define UDPHS_CLRINT_UPSTR_RES (0x1u << 7) 
/* -------- UDPHS_EPTRST : (UDPHS Offset: 0x1C) UDPHS Endpoints Reset Register -------- */
#define UDPHS_EPTRST_EPT_0 (0x1u << 0) 
#define UDPHS_EPTRST_EPT_1 (0x1u << 1) 
#define UDPHS_EPTRST_EPT_2 (0x1u << 2) 
#define UDPHS_EPTRST_EPT_3 (0x1u << 3) 
#define UDPHS_EPTRST_EPT_4 (0x1u << 4) 
#define UDPHS_EPTRST_EPT_5 (0x1u << 5) 
#define UDPHS_EPTRST_EPT_6 (0x1u << 6) 
/* -------- UDPHS_TST : (UDPHS Offset: 0xE0) UDPHS Test Register -------- */
#define UDPHS_TST_SPEED_CFG_Pos 0
#define UDPHS_TST_SPEED_CFG_Msk (0x3u << UDPHS_TST_SPEED_CFG_Pos) 
#define   UDPHS_TST_SPEED_CFG_NORMAL (0x0u << 0) 
#define   UDPHS_TST_SPEED_CFG_HIGH_SPEED (0x2u << 0) 
#define   UDPHS_TST_SPEED_CFG_FULL_SPEED (0x3u << 0) 
#define UDPHS_TST_TST_J (0x1u << 2) 
#define UDPHS_TST_TST_K (0x1u << 3) 
#define UDPHS_TST_TST_PKT (0x1u << 4) 
#define UDPHS_TST_OPMODE2 (0x1u << 5) 
/* -------- UDPHS_IPNAME1 : (UDPHS Offset: 0xF0) UDPHS Name1 Register -------- */
#define UDPHS_IPNAME1_IP_NAME1_Pos 0
#define UDPHS_IPNAME1_IP_NAME1_Msk (0xffffffffu << UDPHS_IPNAME1_IP_NAME1_Pos) 
/* -------- UDPHS_IPNAME2 : (UDPHS Offset: 0xF4) UDPHS Name2 Register -------- */
#define UDPHS_IPNAME2_IP_NAME2_Pos 0
#define UDPHS_IPNAME2_IP_NAME2_Msk (0xffffffffu << UDPHS_IPNAME2_IP_NAME2_Pos) 
/* -------- UDPHS_IPFEATURES : (UDPHS Offset: 0xF8) UDPHS Features Register -------- */
#define UDPHS_IPFEATURES_EPT_NBR_MAX_Pos 0
#define UDPHS_IPFEATURES_EPT_NBR_MAX_Msk (0xfu << UDPHS_IPFEATURES_EPT_NBR_MAX_Pos) 
#define UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Pos 4
#define UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Msk (0x7u << UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Pos) 
#define UDPHS_IPFEATURES_DMA_B_SIZ (0x1u << 7) 
#define UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Pos 8
#define UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Msk (0xfu << UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Pos) 
#define UDPHS_IPFEATURES_FIFO_MAX_SIZE_Pos 12
#define UDPHS_IPFEATURES_FIFO_MAX_SIZE_Msk (0x7u << UDPHS_IPFEATURES_FIFO_MAX_SIZE_Pos) 
#define UDPHS_IPFEATURES_BW_DPRAM (0x1u << 15) 
#define UDPHS_IPFEATURES_DATAB16_8 (0x1u << 16) 
#define UDPHS_IPFEATURES_ISO_EPT_1 (0x1u << 17) 
#define UDPHS_IPFEATURES_ISO_EPT_2 (0x1u << 18) 
#define UDPHS_IPFEATURES_ISO_EPT_3 (0x1u << 19) 
#define UDPHS_IPFEATURES_ISO_EPT_4 (0x1u << 20) 
#define UDPHS_IPFEATURES_ISO_EPT_5 (0x1u << 21) 
#define UDPHS_IPFEATURES_ISO_EPT_6 (0x1u << 22) 
#define UDPHS_IPFEATURES_ISO_EPT_7 (0x1u << 23) 
#define UDPHS_IPFEATURES_ISO_EPT_8 (0x1u << 24) 
#define UDPHS_IPFEATURES_ISO_EPT_9 (0x1u << 25) 
#define UDPHS_IPFEATURES_ISO_EPT_10 (0x1u << 26) 
#define UDPHS_IPFEATURES_ISO_EPT_11 (0x1u << 27) 
#define UDPHS_IPFEATURES_ISO_EPT_12 (0x1u << 28) 
#define UDPHS_IPFEATURES_ISO_EPT_13 (0x1u << 29) 
#define UDPHS_IPFEATURES_ISO_EPT_14 (0x1u << 30) 
#define UDPHS_IPFEATURES_ISO_EPT_15 (0x1u << 31) 
/* -------- UDPHS_EPTCFG : (UDPHS Offset: N/A) UDPHS Endpoint Configuration Register -------- */
#define UDPHS_EPTCFG_EPT_SIZE_Pos 0
#define UDPHS_EPTCFG_EPT_SIZE_Msk (0x7u << UDPHS_EPTCFG_EPT_SIZE_Pos) 
#define   UDPHS_EPTCFG_EPT_SIZE_8 (0x0u << 0) 
#define   UDPHS_EPTCFG_EPT_SIZE_16 (0x1u << 0) 
#define   UDPHS_EPTCFG_EPT_SIZE_32 (0x2u << 0) 
#define   UDPHS_EPTCFG_EPT_SIZE_64 (0x3u << 0) 
#define   UDPHS_EPTCFG_EPT_SIZE_128 (0x4u << 0) 
#define   UDPHS_EPTCFG_EPT_SIZE_256 (0x5u << 0) 
#define   UDPHS_EPTCFG_EPT_SIZE_512 (0x6u << 0) 
#define   UDPHS_EPTCFG_EPT_SIZE_1024 (0x7u << 0) 
#define UDPHS_EPTCFG_EPT_DIR (0x1u << 3) 
#define UDPHS_EPTCFG_EPT_TYPE_Pos 4
#define UDPHS_EPTCFG_EPT_TYPE_Msk (0x3u << UDPHS_EPTCFG_EPT_TYPE_Pos) 
#define   UDPHS_EPTCFG_EPT_TYPE_CTRL8 (0x0u << 4) 
#define   UDPHS_EPTCFG_EPT_TYPE_ISO (0x1u << 4) 
#define   UDPHS_EPTCFG_EPT_TYPE_BULK (0x2u << 4) 
#define   UDPHS_EPTCFG_EPT_TYPE_INT (0x3u << 4) 
#define UDPHS_EPTCFG_BK_NUMBER_Pos 6
#define UDPHS_EPTCFG_BK_NUMBER_Msk (0x3u << UDPHS_EPTCFG_BK_NUMBER_Pos) 
#define   UDPHS_EPTCFG_BK_NUMBER_0 (0x0u << 6) 
#define   UDPHS_EPTCFG_BK_NUMBER_1 (0x1u << 6) 
#define   UDPHS_EPTCFG_BK_NUMBER_2 (0x2u << 6) 
#define   UDPHS_EPTCFG_BK_NUMBER_3 (0x3u << 6) 
#define UDPHS_EPTCFG_NB_TRANS_Pos 8
#define UDPHS_EPTCFG_NB_TRANS_Msk (0x3u << UDPHS_EPTCFG_NB_TRANS_Pos) 
#define UDPHS_EPTCFG_NB_TRANS(value) ((UDPHS_EPTCFG_NB_TRANS_Msk & ((value) << UDPHS_EPTCFG_NB_TRANS_Pos)))
#define UDPHS_EPTCFG_EPT_MAPD (0x1u << 31) 
/* -------- UDPHS_EPTCTLENB : (UDPHS Offset: N/A) UDPHS Endpoint Control Enable Register -------- */
#define UDPHS_EPTCTLENB_EPT_ENABL (0x1u << 0) 
#define UDPHS_EPTCTLENB_AUTO_VALID (0x1u << 1) 
#define UDPHS_EPTCTLENB_INTDIS_DMA (0x1u << 3) 
#define UDPHS_EPTCTLENB_NYET_DIS (0x1u << 4) 
#define UDPHS_EPTCTLENB_DATAX_RX (0x1u << 6) 
#define UDPHS_EPTCTLENB_MDATA_RX (0x1u << 7) 
#define UDPHS_EPTCTLENB_ERR_OVFLW (0x1u << 8) 
#define UDPHS_EPTCTLENB_RX_BK_RDY (0x1u << 9) 
#define UDPHS_EPTCTLENB_TX_COMPLT (0x1u << 10) 
#define UDPHS_EPTCTLENB_TX_PK_RDY (0x1u << 11) 
#define UDPHS_EPTCTLENB_ERR_TRANS (0x1u << 11) 
#define UDPHS_EPTCTLENB_RX_SETUP (0x1u << 12) 
#define UDPHS_EPTCTLENB_ERR_FL_ISO (0x1u << 12) 
#define UDPHS_EPTCTLENB_STALL_SNT (0x1u << 13) 
#define UDPHS_EPTCTLENB_ERR_CRISO (0x1u << 13) 
#define UDPHS_EPTCTLENB_ERR_NBTRA (0x1u << 13) 
#define UDPHS_EPTCTLENB_NAK_IN (0x1u << 14) 
#define UDPHS_EPTCTLENB_ERR_FLUSH (0x1u << 14) 
#define UDPHS_EPTCTLENB_NAK_OUT (0x1u << 15) 
#define UDPHS_EPTCTLENB_BUSY_BANK (0x1u << 18) 
#define UDPHS_EPTCTLENB_SHRT_PCKT (0x1u << 31) 
/* -------- UDPHS_EPTCTLDIS : (UDPHS Offset: N/A) UDPHS Endpoint Control Disable Register -------- */
#define UDPHS_EPTCTLDIS_EPT_DISABL (0x1u << 0) 
#define UDPHS_EPTCTLDIS_AUTO_VALID (0x1u << 1) 
#define UDPHS_EPTCTLDIS_INTDIS_DMA (0x1u << 3) 
#define UDPHS_EPTCTLDIS_NYET_DIS (0x1u << 4) 
#define UDPHS_EPTCTLDIS_DATAX_RX (0x1u << 6) 
#define UDPHS_EPTCTLDIS_MDATA_RX (0x1u << 7) 
#define UDPHS_EPTCTLDIS_ERR_OVFLW (0x1u << 8) 
#define UDPHS_EPTCTLDIS_RX_BK_RDY (0x1u << 9) 
#define UDPHS_EPTCTLDIS_TX_COMPLT (0x1u << 10) 
#define UDPHS_EPTCTLDIS_TX_PK_RDY (0x1u << 11) 
#define UDPHS_EPTCTLDIS_ERR_TRANS (0x1u << 11) 
#define UDPHS_EPTCTLDIS_RX_SETUP (0x1u << 12) 
#define UDPHS_EPTCTLDIS_ERR_FL_ISO (0x1u << 12) 
#define UDPHS_EPTCTLDIS_STALL_SNT (0x1u << 13) 
#define UDPHS_EPTCTLDIS_ERR_CRISO (0x1u << 13) 
#define UDPHS_EPTCTLDIS_ERR_NBTRA (0x1u << 13) 
#define UDPHS_EPTCTLDIS_NAK_IN (0x1u << 14) 
#define UDPHS_EPTCTLDIS_ERR_FLUSH (0x1u << 14) 
#define UDPHS_EPTCTLDIS_NAK_OUT (0x1u << 15) 
#define UDPHS_EPTCTLDIS_BUSY_BANK (0x1u << 18) 
#define UDPHS_EPTCTLDIS_SHRT_PCKT (0x1u << 31) 
/* -------- UDPHS_EPTCTL : (UDPHS Offset: N/A) UDPHS Endpoint Control Register -------- */
#define UDPHS_EPTCTL_EPT_ENABL (0x1u << 0) 
#define UDPHS_EPTCTL_AUTO_VALID (0x1u << 1) 
#define UDPHS_EPTCTL_INTDIS_DMA (0x1u << 3) 
#define UDPHS_EPTCTL_NYET_DIS (0x1u << 4) 
#define UDPHS_EPTCTL_DATAX_RX (0x1u << 6) 
#define UDPHS_EPTCTL_MDATA_RX (0x1u << 7) 
#define UDPHS_EPTCTL_ERR_OVFLW (0x1u << 8) 
#define UDPHS_EPTCTL_RX_BK_RDY (0x1u << 9) 
#define UDPHS_EPTCTL_TX_COMPLT (0x1u << 10) 
#define UDPHS_EPTCTL_TX_PK_RDY (0x1u << 11) 
#define UDPHS_EPTCTL_ERR_TRANS (0x1u << 11) 
#define UDPHS_EPTCTL_RX_SETUP (0x1u << 12) 
#define UDPHS_EPTCTL_ERR_FL_ISO (0x1u << 12) 
#define UDPHS_EPTCTL_STALL_SNT (0x1u << 13) 
#define UDPHS_EPTCTL_ERR_CRISO (0x1u << 13) 
#define UDPHS_EPTCTL_ERR_NBTRA (0x1u << 13) 
#define UDPHS_EPTCTL_NAK_IN (0x1u << 14) 
#define UDPHS_EPTCTL_ERR_FLUSH (0x1u << 14) 
#define UDPHS_EPTCTL_NAK_OUT (0x1u << 15) 
#define UDPHS_EPTCTL_BUSY_BANK (0x1u << 18) 
#define UDPHS_EPTCTL_SHRT_PCKT (0x1u << 31) 
/* -------- UDPHS_EPTSETSTA : (UDPHS Offset: N/A) UDPHS Endpoint Set Status Register -------- */
#define UDPHS_EPTSETSTA_FRCESTALL (0x1u << 5) 
#define UDPHS_EPTSETSTA_KILL_BANK (0x1u << 9) 
#define UDPHS_EPTSETSTA_TX_PK_RDY (0x1u << 11) 
/* -------- UDPHS_EPTCLRSTA : (UDPHS Offset: N/A) UDPHS Endpoint Clear Status Register -------- */
#define UDPHS_EPTCLRSTA_FRCESTALL (0x1u << 5) 
#define UDPHS_EPTCLRSTA_TOGGLESQ (0x1u << 6) 
#define UDPHS_EPTCLRSTA_RX_BK_RDY (0x1u << 9) 
#define UDPHS_EPTCLRSTA_TX_COMPLT (0x1u << 10) 
#define UDPHS_EPTCLRSTA_RX_SETUP (0x1u << 12) 
#define UDPHS_EPTCLRSTA_ERR_FL_ISO (0x1u << 12) 
#define UDPHS_EPTCLRSTA_STALL_SNT (0x1u << 13) 
#define UDPHS_EPTCLRSTA_ERR_NBTRA (0x1u << 13) 
#define UDPHS_EPTCLRSTA_NAK_IN (0x1u << 14) 
#define UDPHS_EPTCLRSTA_ERR_FLUSH (0x1u << 14) 
#define UDPHS_EPTCLRSTA_NAK_OUT (0x1u << 15) 
/* -------- UDPHS_EPTSTA : (UDPHS Offset: N/A) UDPHS Endpoint Status Register -------- */
#define UDPHS_EPTSTA_FRCESTALL (0x1u << 5) 
#define UDPHS_EPTSTA_TOGGLESQ_STA_Pos 6
#define UDPHS_EPTSTA_TOGGLESQ_STA_Msk (0x3u << UDPHS_EPTSTA_TOGGLESQ_STA_Pos) 
#define   UDPHS_EPTSTA_TOGGLESQ_STA_DATA0 (0x0u << 6) 
#define   UDPHS_EPTSTA_TOGGLESQ_STA_DATA1 (0x1u << 6) 
#define   UDPHS_EPTSTA_TOGGLESQ_STA_DATA2 (0x2u << 6) 
#define   UDPHS_EPTSTA_TOGGLESQ_STA_MDATA (0x3u << 6) 
#define UDPHS_EPTSTA_ERR_OVFLW (0x1u << 8) 
#define UDPHS_EPTSTA_RX_BK_RDY (0x1u << 9) 
#define UDPHS_EPTSTA_KILL_BANK (0x1u << 9) 
#define UDPHS_EPTSTA_TX_COMPLT (0x1u << 10) 
#define UDPHS_EPTSTA_TX_PK_RDY (0x1u << 11) 
#define UDPHS_EPTSTA_ERR_TRANS (0x1u << 11) 
#define UDPHS_EPTSTA_RX_SETUP (0x1u << 12) 
#define UDPHS_EPTSTA_ERR_FL_ISO (0x1u << 12) 
#define UDPHS_EPTSTA_STALL_SNT (0x1u << 13) 
#define UDPHS_EPTSTA_ERR_CRISO (0x1u << 13) 
#define UDPHS_EPTSTA_ERR_NBTRA (0x1u << 13) 
#define UDPHS_EPTSTA_NAK_IN (0x1u << 14) 
#define UDPHS_EPTSTA_ERR_FLUSH (0x1u << 14) 
#define UDPHS_EPTSTA_NAK_OUT (0x1u << 15) 
#define UDPHS_EPTSTA_CURRENT_BANK_Pos 16
#define UDPHS_EPTSTA_CURRENT_BANK_Msk (0x3u << UDPHS_EPTSTA_CURRENT_BANK_Pos) 
#define UDPHS_EPTSTA_CONTROL_DIR_Pos 16
#define UDPHS_EPTSTA_CONTROL_DIR_Msk (0x3u << UDPHS_EPTSTA_CONTROL_DIR_Pos) 
#define UDPHS_EPTSTA_BUSY_BANK_STA_Pos 18
#define UDPHS_EPTSTA_BUSY_BANK_STA_Msk (0x3u << UDPHS_EPTSTA_BUSY_BANK_STA_Pos) 
#define   UDPHS_EPTSTA_BUSY_BANK_STA_1BUSYBANK (0x0u << 18) 
#define   UDPHS_EPTSTA_BUSY_BANK_STA_2BUSYBANKS (0x1u << 18) 
#define   UDPHS_EPTSTA_BUSY_BANK_STA_3BUSYBANKS (0x2u << 18) 
#define UDPHS_EPTSTA_BYTE_COUNT_Pos 20
#define UDPHS_EPTSTA_BYTE_COUNT_Msk (0x7ffu << UDPHS_EPTSTA_BYTE_COUNT_Pos) 
#define UDPHS_EPTSTA_SHRT_PCKT (0x1u << 31) 
/* -------- UDPHS_DMANXTDSC : (UDPHS Offset: N/A) UDPHS DMA Next Descriptor Address Register -------- */
#define UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos 0
#define UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos) 
#define UDPHS_DMANXTDSC_NXT_DSC_ADD(value) ((UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos)))
/* -------- UDPHS_DMAADDRESS : (UDPHS Offset: N/A) UDPHS DMA Channel Address Register -------- */
#define UDPHS_DMAADDRESS_BUFF_ADD_Pos 0
#define UDPHS_DMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UDPHS_DMAADDRESS_BUFF_ADD_Pos) 
#define UDPHS_DMAADDRESS_BUFF_ADD(value) ((UDPHS_DMAADDRESS_BUFF_ADD_Msk & ((value) << UDPHS_DMAADDRESS_BUFF_ADD_Pos)))
/* -------- UDPHS_DMACONTROL : (UDPHS Offset: N/A) UDPHS DMA Channel Control Register -------- */
#define UDPHS_DMACONTROL_CHANN_ENB (0x1u << 0) 
#define UDPHS_DMACONTROL_LDNXT_DSC (0x1u << 1) 
#define UDPHS_DMACONTROL_END_TR_EN (0x1u << 2) 
#define UDPHS_DMACONTROL_END_B_EN (0x1u << 3) 
#define UDPHS_DMACONTROL_END_TR_IT (0x1u << 4) 
#define UDPHS_DMACONTROL_END_BUFFIT (0x1u << 5) 
#define UDPHS_DMACONTROL_DESC_LD_IT (0x1u << 6) 
#define UDPHS_DMACONTROL_BURST_LCK (0x1u << 7) 
#define UDPHS_DMACONTROL_BUFF_LENGTH_Pos 16
#define UDPHS_DMACONTROL_BUFF_LENGTH_Msk (0xffffu << UDPHS_DMACONTROL_BUFF_LENGTH_Pos) 
#define UDPHS_DMACONTROL_BUFF_LENGTH(value) ((UDPHS_DMACONTROL_BUFF_LENGTH_Msk & ((value) << UDPHS_DMACONTROL_BUFF_LENGTH_Pos)))
/* -------- UDPHS_DMASTATUS : (UDPHS Offset: N/A) UDPHS DMA Channel Status Register -------- */
#define UDPHS_DMASTATUS_CHANN_ENB (0x1u << 0) 
#define UDPHS_DMASTATUS_CHANN_ACT (0x1u << 1) 
#define UDPHS_DMASTATUS_END_TR_ST (0x1u << 4) 
#define UDPHS_DMASTATUS_END_BF_ST (0x1u << 5) 
#define UDPHS_DMASTATUS_DESC_LDST (0x1u << 6) 
#define UDPHS_DMASTATUS_BUFF_COUNT_Pos 16
#define UDPHS_DMASTATUS_BUFF_COUNT_Msk (0xffffu << UDPHS_DMASTATUS_BUFF_COUNT_Pos) 
#define UDPHS_DMASTATUS_BUFF_COUNT(value) ((UDPHS_DMASTATUS_BUFF_COUNT_Msk & ((value) << UDPHS_DMASTATUS_BUFF_COUNT_Pos)))

#endif /* _SAM3U_UDPHS_COMPONENT_ */