30 #ifndef DACC_H_INCLUDED 31 #define DACC_H_INCLUDED 44 typedef enum dacc_rc {
50 # define DACC_RESOLUTION 10 53 # define DACC_RESOLUTION 12 56 #define DACC_MAX_DATA ((1 << DACC_RESOLUTION) - 1) 59 void dacc_reset(
Dacc *p_dacc);
60 uint32_t dacc_set_trigger(
Dacc *p_dacc, uint32_t ul_trigger);
61 void dacc_disable_trigger(
Dacc *p_dacc);
62 uint32_t dacc_set_transfer_mode(
Dacc *p_dacc, uint32_t ul_mode);
63 void dacc_enable_interrupt(
Dacc *p_dacc, uint32_t ul_interrupt_mask);
64 void dacc_disable_interrupt(
Dacc *p_dacc, uint32_t ul_interrupt_mask);
65 uint32_t dacc_get_interrupt_mask(
Dacc *p_dacc);
66 uint32_t dacc_get_interrupt_status(
Dacc *p_dacc);
67 void dacc_write_conversion_data(
Dacc *p_dacc, uint32_t ul_data);
68 void dacc_set_writeprotect(
Dacc *p_dacc, uint32_t ul_enable);
69 uint32_t dacc_get_writeprotect_status(
Dacc *p_dacc);
70 Pdc *dacc_get_pdc_base(
Dacc *p_dacc);
72 #if (SAM3N_SERIES) || defined(__DOXYGEN__) 73 void dacc_enable(
Dacc *p_dacc);
74 void dacc_disable(
Dacc *p_dacc);
75 uint32_t dacc_set_timing(
Dacc *p_dacc, uint32_t ul_startup,
76 uint32_t ul_clock_divider);
79 #if (SAM3S_SERIES) || (SAM3XA_SERIES) || (SAM4S_SERIES) || defined(__DOXYGEN__) 80 uint32_t dacc_set_channel_selection(
Dacc *p_dacc, uint32_t ul_channel);
81 void dacc_enable_flexible_selection(
Dacc *p_dacc);
83 uint32_t dacc_set_power_save(
Dacc *p_dacc, uint32_t ul_sleep_mode,
84 uint32_t ul_fast_wakeup_mode);
85 uint32_t dacc_set_timing(
Dacc *p_dacc, uint32_t ul_refresh, uint32_t ul_maxs,
87 uint32_t dacc_enable_channel(
Dacc *p_dacc, uint32_t ul_channel);
88 uint32_t dacc_disable_channel(
Dacc *p_dacc, uint32_t ul_channel);
89 uint32_t dacc_get_channel_status(
Dacc *p_dacc);
90 uint32_t dacc_set_analog_control(
Dacc *p_dacc, uint32_t ul_analog_control);
91 uint32_t dacc_get_analog_control(
Dacc *p_dacc);
Pdc hardware registers.
Definition: component_pdc.h:41
Dacc hardware registers.
Definition: component_dacc.h:41