emac.h

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#ifndef EMAC_H_INCLUDED
#define EMAC_H_INCLUDED

#include "../chip.h"
//#include "conf_eth.h"


#ifdef __cplusplus
extern "C" {
#endif


#define EMAC_RXD_ADDR_MASK      0xFFFFFFFC
#define EMAC_RXD_WRAP         (1ul << 1)  
#define EMAC_RXD_OWNERSHIP    (1ul << 0)  
#define EMAC_RXD_BROADCAST    (1ul << 31) 
#define EMAC_RXD_MULTIHASH    (1ul << 30) 
#define EMAC_RXD_UNIHASH      (1ul << 29) 
#define EMAC_RXD_EXTADDR      (1ul << 28) 
#define EMAC_RXD_ADDR1        (1ul << 26) 
#define EMAC_RXD_ADDR2        (1ul << 25) 
#define EMAC_RXD_ADDR3        (1ul << 24) 
#define EMAC_RXD_ADDR4        (1ul << 23) 
#define EMAC_RXD_TYPE         (1ul << 22) 
#define EMAC_RXD_VLAN         (1ul << 21) 
#define EMAC_RXD_PRIORITY     (1ul << 20) 
#define EMAC_RXD_PRIORITY_MASK  (3ul << 17) 
#define EMAC_RXD_CFI          (1ul << 16) 
#define EMAC_RXD_EOF          (1ul << 15) 
#define EMAC_RXD_SOF          (1ul << 14) 
#define EMAC_RXD_OFFSET_MASK                
#define EMAC_RXD_LEN_MASK       (0xFFF)     
#define EMAC_RXD_LENJUMBO_MASK  (0x3FFF)    
#define EMAC_TXD_USED         (1ul << 31) 
#define EMAC_TXD_WRAP         (1ul << 30) 
#define EMAC_TXD_ERROR        (1ul << 29) 
#define EMAC_TXD_UNDERRUN     (1ul << 28) 
#define EMAC_TXD_EXHAUSTED    (1ul << 27) 
#define EMAC_TXD_NOCRC        (1ul << 16) 
#define EMAC_TXD_LAST         (1ul << 15) 
#define EMAC_TXD_LEN_MASK       (0x7FF)     
#define EMAC_FRAME_LENTGH_MAX       1536

#define EMAC_RX_UNITSIZE            128     
#define EMAC_TX_UNITSIZE            1518    
#define EMAC_CLOCK_SPEED_160MHZ        (160*1000*1000)
#define EMAC_CLOCK_SPEED_80MHZ          (80*1000*1000)
#define EMAC_CLOCK_SPEED_40MHZ          (40*1000*1000)
#define EMAC_CLOCK_SPEED_20MHZ          (20*1000*1000)

#define EMAC_MAN_CODE_VALUE    (10)

#define EMAC_MAN_SOF_VALUE     (1)

#define EMAC_MAN_RW_TYPE       (2)

#define EMAC_MAN_READ_ONLY     (1)

#define EMAC_ADDR_LENGTH       (6)

typedef enum {
    EMAC_OK = 0,         
    EMAC_TIMEOUT = 1,    
    EMAC_TX_BUSY,        
    EMAC_RX_NULL,        
    EMAC_SIZE_TOO_SMALL, 
    EMAC_PARAM,          
    EMAC_INVALID = 0xFF, /* Invalid */
} emac_status_t;

#if defined __ICCARM__
#pragma pack(4)    /* IAR */
#define __attribute__(...)    /* IAR */
#endif /* IAR */

typedef struct emac_rx_descriptor {
    union emac_rx_addr {
        uint32_t val;
        struct emac_rx_addr_bm {
            uint32_t b_ownership:1, 
            b_wrap:1,   
            addr_dw:30; 
        } bm;
    } addr; 
    union emac_rx_status {
        uint32_t val;
        struct emac_rx_status_bm {
            uint32_t len:12,       
            offset:2,              
            b_sof:1,               
            b_eof:1,               
            b_cfi:1,               
            vlan_priority:3,       
            b_priority_detected:1, 
            b_vlan_detected:1,     
            b_type_id_match:1,     
            b_addr4match:1,        
            b_addr3match:1,        
            b_addr2match:1,        
            b_addr1match:1,        
            reserved:1,
            b_ext_addr_match:1,    
            b_uni_hash_match:1,    
            b_multi_hash_match:1,  
            b_boardcast_detect:1;  
        } bm;
    } status;
} __attribute__ ((packed, aligned(8))) emac_rx_descriptor_t; /* GCC */

typedef struct emac_tx_descriptor {
    uint32_t addr;
    union emac_tx_status {
        uint32_t val;
        struct emac_tx_status_bm {
            uint32_t len:11, 
            reserved:4,
            b_last_buffer:1, 
            b_no_crc:1,      
            reserved1:10,
            b_exhausted:1,   
            b_underrun:1,    
            b_error:1,       
            b_wrap:1,        
            b_used:1;        
        } bm;
    } status;
} __attribute__ ((packed, aligned(8))) emac_tx_descriptor_t; /* GCC */

#ifdef __ICCARM__ /* IAR */
#pragma pack()
#endif

typedef struct emac_options {
    /*  Enable/Disable CopyAllFrame */
    uint8_t uc_copy_all_frame;
    /* Enable/Disable NoBroadCast */
    uint8_t uc_no_boardcast;
    /* MAC address */
    uint8_t uc_mac_addr[EMAC_ADDR_LENGTH];
} emac_options_t;

typedef void (*emac_dev_tx_cb_t) (uint32_t ul_status);
typedef void (*emac_dev_wakeup_cb_t) (void);

typedef struct emac_device {

    Emac *p_hw;
    uint8_t *p_tx_buffer;
    uint8_t *p_rx_buffer;
    emac_rx_descriptor_t *p_rx_dscr;
    emac_tx_descriptor_t *p_tx_dscr;
    emac_dev_tx_cb_t func_rx_cb;
    emac_dev_wakeup_cb_t func_wakeup_cb;
    emac_dev_tx_cb_t *func_tx_cb_list;
    uint16_t us_rx_list_size;
    uint16_t us_rx_idx;
    uint16_t us_tx_list_size;
    uint16_t us_tx_head;
    uint16_t us_tx_tail;

    uint8_t uc_wakeup_threshold;
} emac_device_t;

static inline void emac_network_control(Emac* p_emac, uint32_t ul_ncr)
{
    p_emac->EMAC_NCR = ul_ncr;
}

static inline uint32_t emac_get_network_control(Emac* p_emac)
{
    return p_emac->EMAC_NCR;
}

static inline void emac_enable_receive(Emac* p_emac, uint8_t uc_enable)
{
    if (uc_enable) {
        p_emac->EMAC_NCR |= EMAC_NCR_RE;
    } else {
        p_emac->EMAC_NCR &= ~EMAC_NCR_RE;
    }
}

static inline void emac_enable_transmit(Emac* p_emac, uint8_t uc_enable)
{
    if (uc_enable) {
        p_emac->EMAC_NCR |= EMAC_NCR_TE;
    } else {
        p_emac->EMAC_NCR &= ~EMAC_NCR_TE;
    }
}

static inline void emac_enable_management(Emac* p_emac, uint8_t uc_enable)
{
    if (uc_enable) {
        p_emac->EMAC_NCR |= EMAC_NCR_MPE;
    } else {
        p_emac->EMAC_NCR &= ~EMAC_NCR_MPE;
    }
}

static inline void emac_clear_statistics(Emac* p_emac)
{
    p_emac->EMAC_NCR |= EMAC_NCR_CLRSTAT;
}

static inline void emac_increase_statistics(Emac* p_emac)
{
    p_emac->EMAC_NCR |= EMAC_NCR_INCSTAT;
}

static inline void emac_enable_statistics_write(Emac* p_emac,
        uint8_t uc_enable)
{
    if (uc_enable) {
        p_emac->EMAC_NCR |= EMAC_NCR_WESTAT;
    } else {
        p_emac->EMAC_NCR &= ~EMAC_NCR_WESTAT;
    }
}

static inline void emac_enable_back_pressure(Emac* p_emac, uint8_t uc_enable)
{
    if (uc_enable) {
        p_emac->EMAC_NCR |= EMAC_NCR_BP;
    } else {
        p_emac->EMAC_NCR &= ~EMAC_NCR_BP;
    }
}

static inline void emac_start_transmission(Emac* p_emac)
{
    p_emac->EMAC_NCR |= EMAC_NCR_TSTART;
}

static inline void emac_halt_transmission(Emac* p_emac)
{
    p_emac->EMAC_NCR |= EMAC_NCR_THALT;
}

static inline void emac_set_configure(Emac* p_emac, uint32_t ul_cfg)
{
    p_emac->EMAC_NCFGR = ul_cfg;
}

static inline uint32_t emac_get_configure(Emac* p_emac)
{
    return p_emac->EMAC_NCFGR;
}

static inline void emac_set_speed(Emac* p_emac, uint8_t uc_speed)
{
    if (uc_speed) {
        p_emac->EMAC_NCFGR |= EMAC_NCFGR_SPD;
    } else {
        p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_SPD;
    }
}

static inline void emac_enable_full_duplex(Emac* p_emac, uint8_t uc_enable)
{
    if (uc_enable) {
        p_emac->EMAC_NCFGR |= EMAC_NCFGR_FD;
    } else {
        p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_FD;
    }
}

static inline void emac_enable_copy_all(Emac* p_emac, uint8_t uc_enable)
{
    if (uc_enable) {
        p_emac->EMAC_NCFGR |= EMAC_NCFGR_CAF;
    } else {
        p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_CAF;
    }
}

static inline void emac_enable_jumbo_frames(Emac* p_emac, uint8_t uc_enable)
{
    if (uc_enable) {
        p_emac->EMAC_NCFGR |= EMAC_NCFGR_JFRAME;
    } else {
        p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_JFRAME;
    }
}

static inline void emac_disable_broadcast(Emac* p_emac, uint8_t uc_enable)
{
    if (uc_enable) {
        p_emac->EMAC_NCFGR |= EMAC_NCFGR_NBC;
    } else {
        p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_NBC;
    }
}

static inline void emac_enable_multicast_hash(Emac* p_emac, uint8_t uc_enable)
{
    if (uc_enable) {
        p_emac->EMAC_NCFGR |= EMAC_NCFGR_UNI;
    } else {
        p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_UNI;
    }
}

static inline void emac_enable_big_frame(Emac* p_emac, uint8_t uc_enable)
{
    if (uc_enable) {
        p_emac->EMAC_NCFGR |= EMAC_NCFGR_BIG;
    } else {
        p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_BIG;
    }
}

static inline uint8_t emac_set_clock(Emac* p_emac, uint32_t ul_mck)
{
    uint32_t ul_clk;

    if (ul_mck > EMAC_CLOCK_SPEED_160MHZ) {
        return EMAC_INVALID;
    } else if (ul_mck > EMAC_CLOCK_SPEED_80MHZ) {
        ul_clk = EMAC_NCFGR_CLK_MCK_64;
    } else if (ul_mck > EMAC_CLOCK_SPEED_40MHZ) {
        ul_clk = EMAC_NCFGR_CLK_MCK_32;
    } else if (ul_mck > EMAC_CLOCK_SPEED_20MHZ) {
        ul_clk = EMAC_NCFGR_CLK_MCK_16;
    } else {
        ul_clk = EMAC_NCFGR_CLK_MCK_8;
    }

    p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_CLK_Msk;
    p_emac->EMAC_NCFGR |= ul_clk;

    return EMAC_OK;
}

static inline void emac_enable_retry_test(Emac* p_emac, uint8_t uc_enable)
{
    if (uc_enable) {
        p_emac->EMAC_NCFGR |= EMAC_NCFGR_RTY;
    } else {
        p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_RTY;
    }
}

static inline void emac_enable_pause_frame(Emac* p_emac, uint8_t uc_enable)
{
    if (uc_enable) {
        p_emac->EMAC_NCFGR |= EMAC_NCFGR_PAE;
    } else {
        p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_PAE;
    }
}

static inline void emac_set_rx_buffer_offset(Emac* p_emac, uint8_t uc_offset)
{
    p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_RBOF_Msk;
    p_emac->EMAC_NCFGR |=
            (EMAC_NCFGR_RBOF_Msk & ((uc_offset) << EMAC_NCFGR_RBOF_Pos));
}

static inline void emac_enable_rx_length_check(Emac* p_emac, uint8_t uc_enable)
{
    if (uc_enable) {
        p_emac->EMAC_NCFGR |= EMAC_NCFGR_RLCE;
    } else {
        p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_RLCE;
    }
}

static inline void emac_enable_discard_fcs(Emac* p_emac, uint8_t uc_enable)
{
    if (uc_enable) {
        p_emac->EMAC_NCFGR |= EMAC_NCFGR_DRFCS;
    } else {
        p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_DRFCS;
    }
}


static inline void emac_enable_efrhd(Emac* p_emac, uint8_t uc_enable)
{
    if (uc_enable) {
        p_emac->EMAC_NCFGR |= EMAC_NCFGR_EFRHD;
    } else {
        p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_EFRHD;
    }
}

static inline void emac_enable_ignore_rx_fcs(Emac* p_emac, uint8_t uc_enable)
{
    if (uc_enable) {
        p_emac->EMAC_NCFGR |= EMAC_NCFGR_IRXFCS;
    } else {
        p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_IRXFCS;
    }
}

static inline uint32_t emac_get_status(Emac* p_emac)
{
    return p_emac->EMAC_NSR;
}

static inline uint8_t emac_get_MDIO(Emac* p_emac)
{
    return ((p_emac->EMAC_NSR & EMAC_NSR_MDIO) > 0);
}

static inline uint8_t emac_is_phy_idle(Emac* p_emac)
{
    return ((p_emac->EMAC_NSR & EMAC_NSR_IDLE) > 0);
}

static inline uint32_t emac_get_tx_status(Emac* p_emac)
{
    return p_emac->EMAC_TSR;
}

static inline void emac_clear_tx_status(Emac* p_emac, uint32_t ul_status)
{
    p_emac->EMAC_TSR = ul_status;
}

static inline uint32_t emac_get_rx_status(Emac* p_emac)
{
    return p_emac->EMAC_RSR;
}

static inline void emac_clear_rx_status(Emac* p_emac, uint32_t ul_status)
{
    p_emac->EMAC_RSR = ul_status;
}

static inline void emac_set_rx_queue(Emac* p_emac, uint32_t ul_addr)
{
    p_emac->EMAC_RBQP = EMAC_RBQP_ADDR_Msk & ul_addr;
}

static inline uint32_t emac_get_rx_queue(Emac* p_emac)
{
    return p_emac->EMAC_RBQP;
}

static inline void emac_set_tx_queue(Emac* p_emac, uint32_t ul_addr)
{
    p_emac->EMAC_TBQP = EMAC_TBQP_ADDR_Msk & ul_addr;
}

static inline uint32_t emac_get_tx_queue(Emac* p_emac)
{
    return p_emac->EMAC_TBQP;
}

static inline void emac_enable_interrupt(Emac* p_emac, uint32_t ul_source)
{
    p_emac->EMAC_IER = ul_source;
}

static inline void emac_disable_interrupt(Emac* p_emac, uint32_t ul_source)
{
    p_emac->EMAC_IDR = ul_source;
}

static inline uint32_t emac_get_interrupt_status(Emac* p_emac)
{
    return p_emac->EMAC_ISR;
}

static inline uint32_t emac_get_interrupt_mask(Emac* p_emac)
{
    return p_emac->EMAC_IMR;
}

static inline void emac_maintain_phy(Emac* p_emac,
        uint8_t uc_phy_addr, uint8_t uc_reg_addr, uint8_t uc_rw,
        uint16_t us_data)
{
    /* Wait until bus idle */
    while ((p_emac->EMAC_NSR & EMAC_NSR_IDLE) == 0);
    /* Write maintain register */
    p_emac->EMAC_MAN = EMAC_MAN_CODE(EMAC_MAN_CODE_VALUE)
            | EMAC_MAN_SOF(EMAC_MAN_SOF_VALUE)
            | EMAC_MAN_PHYA(uc_phy_addr)
            | EMAC_MAN_REGA(uc_reg_addr)
            | EMAC_MAN_RW((uc_rw ? EMAC_MAN_RW_TYPE : EMAC_MAN_READ_ONLY))
            | EMAC_MAN_DATA(us_data);
}

static inline uint16_t emac_get_phy_data(Emac* p_emac)
{
    /* Wait until bus idle */
    while ((p_emac->EMAC_NSR & EMAC_NSR_IDLE) == 0);
    /* Return data */
    return (uint16_t) (p_emac->EMAC_MAN & EMAC_MAN_DATA_Msk);
}

static inline void emac_set_pause_time(Emac* p_emac, uint16_t us_pause_time)
{
    p_emac->EMAC_PTR = us_pause_time;
}

static inline void emac_set_hash(Emac* p_emac, uint32_t ul_hash_top,
        uint32_t ul_hash_bottom)
{
    p_emac->EMAC_HRB = ul_hash_bottom;
    p_emac->EMAC_HRT = ul_hash_top;
}

static inline void emac_set_hash64(Emac* p_emac, uint64_t ull_hash)
{
    p_emac->EMAC_HRB = (uint32_t) ull_hash;
    p_emac->EMAC_HRT = (uint32_t) (ull_hash >> 32);
}

static inline void emac_set_address(Emac* p_emac, uint8_t uc_index,
        uint8_t* p_mac_addr)
{
    p_emac->EMAC_SA[uc_index].EMAC_SAxB = (p_mac_addr[3] << 24)
            | (p_mac_addr[2] << 16)
            | (p_mac_addr[1] << 8)
            | (p_mac_addr[0]);
    p_emac->EMAC_SA[uc_index].EMAC_SAxT = (p_mac_addr[5] << 8)
            | (p_mac_addr[4]);
}

static inline void emac_set_address32(Emac* p_emac, uint8_t uc_index,
        uint32_t ul_mac_top, uint32_t ul_mac_bottom)
{
    p_emac->EMAC_SA[uc_index].EMAC_SAxB = ul_mac_bottom;
    p_emac->EMAC_SA[uc_index].EMAC_SAxT = ul_mac_top;
}

static inline void emac_set_address64(Emac* p_emac, uint8_t uc_index,
        uint64_t ull_mac)
{
    p_emac->EMAC_SA[uc_index].EMAC_SAxB = (uint32_t) ull_mac;
    p_emac->EMAC_SA[uc_index].EMAC_SAxT = (uint32_t) (ull_mac >> 32);
}

static inline void emac_set_type_id(Emac* p_emac, uint16_t us_type_id)
{
    p_emac->EMAC_TID = EMAC_TID_TID(us_type_id);
}

static inline uint16_t emac_get_type_id(Emac* p_emac)
{
    return (p_emac->EMAC_TID & EMAC_TID_TID_Msk);
}

static inline void emac_enable_rmii(Emac* p_emac, uint8_t uc_enable)
{
    if (uc_enable) {
        p_emac->EMAC_USRIO |= EMAC_USRIO_RMII;
    } else {
        p_emac->EMAC_USRIO &= ~EMAC_USRIO_RMII;
    }
}

static inline void emac_enable_transceiver_clock(Emac* p_emac,
        uint8_t uc_enable)
{
    if (uc_enable) {
        p_emac->EMAC_USRIO |= EMAC_USRIO_CLKEN;
    } else {
        p_emac->EMAC_USRIO &= ~EMAC_USRIO_CLKEN;
    }
}

uint8_t emac_phy_read(Emac* p_emac, uint8_t uc_phy_address, uint8_t uc_address,
        uint32_t* p_value);
uint8_t emac_phy_write(Emac* p_emac, uint8_t uc_phy_address,
        uint8_t uc_address, uint32_t ul_value);
void emac_dev_init(Emac* p_emac, emac_device_t* p_emac_dev,
        emac_options_t* p_opt);
uint32_t emac_dev_read(emac_device_t* p_emac_dev, uint8_t* p_frame,
        uint32_t ul_frame_size, uint32_t* p_rcv_size);
uint32_t emac_dev_write(emac_device_t* p_emac_dev, void *p_buffer,
        uint32_t ul_size, emac_dev_tx_cb_t func_tx_cb);
uint32_t emac_dev_get_tx_load(emac_device_t* p_emac_dev);
void emac_dev_set_rx_callback(emac_device_t* p_emac_dev,
        emac_dev_tx_cb_t func_rx_cb);
uint8_t emac_dev_set_tx_wakeup_callback(emac_device_t* p_emac_dev,
        emac_dev_wakeup_cb_t func_wakeup, uint8_t uc_threshold);
void emac_dev_reset(emac_device_t* p_emac_dev);
void emac_handler(emac_device_t* p_emac_dev);


#ifdef __cplusplus
}
#endif


#endif /* EMAC_H_INCLUDED */