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Classes | Macros
CMSIS ITM
CMSIS Core Register

Classes

struct  ITM_Type
 Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...
 

Macros

#define ITM_TPR_PRIVMASK_Pos   0
 
#define ITM_TPR_PRIVMASK_Msk   (0xFUL << ITM_TPR_PRIVMASK_Pos)
 
#define ITM_TCR_BUSY_Pos   23
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TraceBusID_Pos   16
 
#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPrescale_Pos   8
 
#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
 
#define ITM_TCR_SWOENA_Pos   4
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_TXENA_Pos   3
 
#define ITM_TCR_TXENA_Msk   (1UL << ITM_TCR_TXENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0
 
#define ITM_TCR_ITMENA_Msk   (1UL << ITM_TCR_ITMENA_Pos)
 
#define ITM_TPR_PRIVMASK_Pos   0
 
#define ITM_TPR_PRIVMASK_Msk   (0xFUL << ITM_TPR_PRIVMASK_Pos)
 
#define ITM_TCR_BUSY_Pos   23
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TraceBusID_Pos   16
 
#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPrescale_Pos   8
 
#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
 
#define ITM_TCR_SWOENA_Pos   4
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_TXENA_Pos   3
 
#define ITM_TCR_TXENA_Msk   (1UL << ITM_TCR_TXENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0
 
#define ITM_TCR_ITMENA_Msk   (1UL << ITM_TCR_ITMENA_Pos)
 

Detailed Description

Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)

Macro Definition Documentation

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

#define ITM_TCR_BUSY_Pos   23

ITM TCR: BUSY Position

#define ITM_TCR_BUSY_Pos   23

ITM TCR: BUSY Position

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

#define ITM_TCR_GTSFREQ_Pos   10

ITM TCR: Global timestamp frequency Position

#define ITM_TCR_GTSFREQ_Pos   10

ITM TCR: Global timestamp frequency Position

#define ITM_TCR_ITMENA_Msk   (1UL << ITM_TCR_ITMENA_Pos)

ITM TCR: ITM Enable bit Mask

#define ITM_TCR_ITMENA_Msk   (1UL << ITM_TCR_ITMENA_Pos)

ITM TCR: ITM Enable bit Mask

#define ITM_TCR_ITMENA_Pos   0

ITM TCR: ITM Enable bit Position

#define ITM_TCR_ITMENA_Pos   0

ITM TCR: ITM Enable bit Position

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

#define ITM_TCR_SWOENA_Pos   4

ITM TCR: SWOENA Position

#define ITM_TCR_SWOENA_Pos   4

ITM TCR: SWOENA Position

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

#define ITM_TCR_SYNCENA_Pos   2

ITM TCR: SYNCENA Position

#define ITM_TCR_SYNCENA_Pos   2

ITM TCR: SYNCENA Position

#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

#define ITM_TCR_TraceBusID_Pos   16

ITM TCR: ATBID Position

#define ITM_TCR_TraceBusID_Pos   16

ITM TCR: ATBID Position

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

#define ITM_TCR_TSENA_Pos   1

ITM TCR: TSENA Position

#define ITM_TCR_TSENA_Pos   1

ITM TCR: TSENA Position

#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

#define ITM_TCR_TSPrescale_Pos   8

ITM TCR: TSPrescale Position

#define ITM_TCR_TSPrescale_Pos   8

ITM TCR: TSPrescale Position

#define ITM_TCR_TXENA_Msk   (1UL << ITM_TCR_TXENA_Pos)

ITM TCR: TXENA Mask

#define ITM_TCR_TXENA_Msk   (1UL << ITM_TCR_TXENA_Pos)

ITM TCR: TXENA Mask

#define ITM_TCR_TXENA_Pos   3

ITM TCR: TXENA Position

#define ITM_TCR_TXENA_Pos   3

ITM TCR: TXENA Position

#define ITM_TPR_PRIVMASK_Msk   (0xFUL << ITM_TPR_PRIVMASK_Pos)

ITM TPR: PRIVMASK Mask

#define ITM_TPR_PRIVMASK_Msk   (0xFUL << ITM_TPR_PRIVMASK_Pos)

ITM TPR: PRIVMASK Mask

#define ITM_TPR_PRIVMASK_Pos   0

ITM TPR: PRIVMASK Position

#define ITM_TPR_PRIVMASK_Pos   0

ITM TPR: PRIVMASK Position