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SAM3N1C definitions

Modules

 CMSIS Definitions
 
 Peripheral Software API
 
 Registers Access Definitions
 
 Peripheral Ids Definitions
 
 Peripheral Base Address Definitions
 
 Peripheral Pio Definitions
 

Macros

#define IFLASH_SIZE   (0x10000u)
 
#define IFLASH_PAGE_SIZE   (256u)
 
#define IFLASH_LOCK_REGION_SIZE   (16384u)
 
#define IFLASH_NB_OF_PAGES   (256u)
 
#define IFLASH_NB_OF_LOCK_BITS   (4u)
 
#define IRAM_SIZE   (0x2000u)
 
#define IFLASH_ADDR   (0x00400000u)
 
#define IROM_ADDR   (0x00800000u)
 
#define IRAM_ADDR   (0x20000000u)
 
#define CHIP_FREQ_SLCK_RC_MIN   (20000UL)
 
#define CHIP_FREQ_SLCK_RC   (32000UL)
 
#define CHIP_FREQ_SLCK_RC_MAX   (44000UL)
 
#define CHIP_FREQ_MAINCK_RC_4MHZ   (4000000UL)
 
#define CHIP_FREQ_MAINCK_RC_8MHZ   (8000000UL)
 
#define CHIP_FREQ_MAINCK_RC_12MHZ   (12000000UL)
 
#define CHIP_FREQ_CPU_MAX   (48000000UL)
 
#define CHIP_FREQ_XTAL_32K   (32768UL)
 
#define CHIP_FREQ_XTAL_12M   (12000000UL)
 
#define CHIP_FLASH_WRITE_WAIT_STATE   (6U)
 
#define CHIP_FREQ_FWS_0   (21000000UL)
 Maximum operating frequency when FWS is 0.
 
#define CHIP_FREQ_FWS_1   (32000000UL)
 Maximum operating frequency when FWS is 1.
 
#define CHIP_FREQ_FWS_2   (48000000UL)
 Maximum operating frequency when FWS is 2.
 

Typedefs

typedef volatile const uint32_t RoReg
 
typedef volatile uint32_t WoReg
 
typedef volatile uint32_t RwReg
 

Detailed Description

This file defines all structures and symbols for SAM3N1C:

Macro Definition Documentation

#define IFLASH_ADDR   (0x00400000u)

Internal Flash base address

#define IRAM_ADDR   (0x20000000u)

Internal RAM base address

#define IROM_ADDR   (0x00800000u)

Internal ROM base address

Typedef Documentation

typedef volatile const uint32_t RoReg

Read only 32-bit register (volatile const unsigned int)

typedef volatile uint32_t RwReg

Read-Write 32-bit register (volatile unsigned int)

typedef volatile uint32_t WoReg

Write only 32-bit register (volatile unsigned int)