Modules
	CMSIS Definitions

	Peripheral Software API

	Registers Access Definitions

	Peripheral Ids Definitions

	Peripheral Base Address Definitions

	Peripheral Pio Definitions

Macros
#define	IFLASH0_SIZE (0x80000u)

#define	IFLASH0_PAGE_SIZE (256u)

#define	IFLASH0_LOCK_REGION_SIZE (16384u)

#define	IFLASH0_NB_OF_PAGES (2048u)

#define	IFLASH0_NB_OF_LOCK_BITS (16u)

#define	IRAM_SIZE (0x10000u)

#define	IFLASH_SIZE (IFLASH0_SIZE)

#define	IFLASH_ADDR (0x00400000u)

#define	IFLASH0_ADDR (0x00400000u)

#define	IROM_ADDR (0x00800000u)

#define	IRAM_ADDR (0x20000000u)

#define	EBI_CS0_ADDR (0x60000000u)

#define	EBI_CS1_ADDR (0x61000000u)

#define	EBI_CS2_ADDR (0x62000000u)

#define	EBI_CS3_ADDR (0x63000000u)

#define	CHIP_FREQ_SLCK_RC_MIN (20000UL)

#define	CHIP_FREQ_SLCK_RC (32000UL)

#define	CHIP_FREQ_SLCK_RC_MAX (44000UL)

#define	CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)

#define	CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)

#define	CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)

#define	CHIP_FREQ_CPU_MAX (64000000UL)

#define	CHIP_FREQ_XTAL_32K (32768UL)

#define	CHIP_FREQ_XTAL_12M (12000000UL)

#define	CHIP_FLASH_WRITE_WAIT_STATE (6U)

#define	CHIP_FREQ_FWS_0 (21000000UL)
	Maximum operating frequency when FWS is 0.

#define	CHIP_FREQ_FWS_1 (35000000UL)
	Maximum operating frequency when FWS is 1.

#define	CHIP_FREQ_FWS_2 (60000000UL)
	Maximum operating frequency when FWS is 2.

#define	CHIP_FREQ_FWS_3 (64000000UL)
	Maximum operating frequency when FWS is 3.

Typedefs
typedef volatile const uint32_t	RoReg

typedef volatile uint32_t	WoReg

typedef volatile uint32_t	RwReg

Detailed Description

This file defines all structures and symbols for SAM3S8B:

Macro Definition Documentation

#define EBI_CS0_ADDR (0x60000000u)

EBI Chip Select 0 base address

#define EBI_CS1_ADDR (0x61000000u)

EBI Chip Select 1 base address

#define EBI_CS2_ADDR (0x62000000u)

EBI Chip Select 2 base address

#define EBI_CS3_ADDR (0x63000000u)

EBI Chip Select 3 base address

#define IFLASH0_ADDR (0x00400000u)

Internal Flash 0 base address

#define IFLASH_ADDR (0x00400000u)

Internal Flash base address

#define IRAM_ADDR (0x20000000u)

Internal RAM base address

#define IROM_ADDR (0x00800000u)

Internal ROM base address

typedef volatile const uint32_t RoReg

Read only 32-bit register (volatile const unsigned int)

typedef volatile uint32_t RwReg

Read-Write 32-bit register (volatile unsigned int)

typedef volatile uint32_t WoReg

Write only 32-bit register (volatile unsigned int)