Classes
struct	Adc12b
	Adc12b hardware registers. More...

Macros
#define	ADC12B_CR_SWRST (0x1u << 0)
	(ADC12B_CR) Software Reset

#define	ADC12B_CR_START (0x1u << 1)
	(ADC12B_CR) Start Conversion

#define	ADC12B_MR_TRGEN (0x1u << 0)
	(ADC12B_MR) Trigger Enable

#define	ADC12B_MR_TRGEN_DIS (0x0u << 0)
	(ADC12B_MR) Hardware triggers are disabled. Starting a conversion is only possible by software.

#define	ADC12B_MR_TRGEN_EN (0x1u << 0)
	(ADC12B_MR) Hardware trigger selected by TRGSEL field is enabled.

#define	ADC12B_MR_TRGSEL_Pos 1

#define	ADC12B_MR_TRGSEL_Msk (0x7u << ADC12B_MR_TRGSEL_Pos)
	(ADC12B_MR) Trigger Selection

#define	ADC12B_MR_TRGSEL(value) ((ADC12B_MR_TRGSEL_Msk & ((value) << ADC12B_MR_TRGSEL_Pos)))

#define	ADC12B_MR_TRGSEL_ADC_TRIG0 (0x0u << 1)
	(ADC12B_MR) External trigger

#define	ADC12B_MR_TRGSEL_ADC_TRIG1 (0x1u << 1)
	(ADC12B_MR) TIO Output of the Timer Counter Channel 0

#define	ADC12B_MR_TRGSEL_ADC_TRIG2 (0x2u << 1)
	(ADC12B_MR) TIO Output of the Timer Counter Channel 1

#define	ADC12B_MR_TRGSEL_ADC_TRIG3 (0x3u << 1)
	(ADC12B_MR) TIO Output of the Timer Counter Channel 2

#define	ADC12B_MR_TRGSEL_ADC_TRIG4 (0x4u << 1)
	(ADC12B_MR) PWM Event Line 0

#define	ADC12B_MR_TRGSEL_ADC_TRIG5 (0x5u << 1)
	(ADC12B_MR) PWM Event Line 1

#define	ADC12B_MR_LOWRES (0x1u << 4)
	(ADC12B_MR) Resolution

#define	ADC12B_MR_LOWRES_BITS_12 (0x0u << 4)
	(ADC12B_MR) 12-bit resolution

#define	ADC12B_MR_LOWRES_BITS_10 (0x1u << 4)
	(ADC12B_MR) 10-bit resolution

#define	ADC12B_MR_SLEEP (0x1u << 5)
	(ADC12B_MR) Sleep Mode

#define	ADC12B_MR_SLEEP_NORMAL (0x0u << 5)
	(ADC12B_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions

#define	ADC12B_MR_SLEEP_SLEEP (0x1u << 5)
	(ADC12B_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions

#define	ADC12B_MR_PRESCAL_Pos 8

#define	ADC12B_MR_PRESCAL_Msk (0xffu << ADC12B_MR_PRESCAL_Pos)
	(ADC12B_MR) Prescaler Rate Selection

#define	ADC12B_MR_PRESCAL(value) ((ADC12B_MR_PRESCAL_Msk & ((value) << ADC12B_MR_PRESCAL_Pos)))

#define	ADC12B_MR_STARTUP_Pos 16

#define	ADC12B_MR_STARTUP_Msk (0xffu << ADC12B_MR_STARTUP_Pos)
	(ADC12B_MR) Start Up Time

#define	ADC12B_MR_STARTUP(value) ((ADC12B_MR_STARTUP_Msk & ((value) << ADC12B_MR_STARTUP_Pos)))

#define	ADC12B_MR_SHTIM_Pos 24

#define	ADC12B_MR_SHTIM_Msk (0xfu << ADC12B_MR_SHTIM_Pos)
	(ADC12B_MR) Sample & Hold Time

#define	ADC12B_MR_SHTIM(value) ((ADC12B_MR_SHTIM_Msk & ((value) << ADC12B_MR_SHTIM_Pos)))

#define	ADC12B_CHER_CH0 (0x1u << 0)
	(ADC12B_CHER) Channel 0 Enable

#define	ADC12B_CHER_CH1 (0x1u << 1)
	(ADC12B_CHER) Channel 1 Enable

#define	ADC12B_CHER_CH2 (0x1u << 2)
	(ADC12B_CHER) Channel 2 Enable

#define	ADC12B_CHER_CH3 (0x1u << 3)
	(ADC12B_CHER) Channel 3 Enable

#define	ADC12B_CHER_CH4 (0x1u << 4)
	(ADC12B_CHER) Channel 4 Enable

#define	ADC12B_CHER_CH5 (0x1u << 5)
	(ADC12B_CHER) Channel 5 Enable

#define	ADC12B_CHER_CH6 (0x1u << 6)
	(ADC12B_CHER) Channel 6 Enable

#define	ADC12B_CHER_CH7 (0x1u << 7)
	(ADC12B_CHER) Channel 7 Enable

#define	ADC12B_CHDR_CH0 (0x1u << 0)
	(ADC12B_CHDR)

#define	ADC12B_CHDR_CH1 (0x1u << 1)
	(ADC12B_CHDR)

#define	ADC12B_CHDR_CH2 (0x1u << 2)
	(ADC12B_CHDR)

#define	ADC12B_CHDR_CH3 (0x1u << 3)
	(ADC12B_CHDR)

#define	ADC12B_CHDR_CH4 (0x1u << 4)
	(ADC12B_CHDR)

#define	ADC12B_CHDR_CH5 (0x1u << 5)
	(ADC12B_CHDR)

#define	ADC12B_CHDR_CH6 (0x1u << 6)
	(ADC12B_CHDR)

#define	ADC12B_CHDR_CH7 (0x1u << 7)
	(ADC12B_CHDR)

#define	ADC12B_CHSR_CH0 (0x1u << 0)
	(ADC12B_CHSR) Channel 0 Status

#define	ADC12B_CHSR_CH1 (0x1u << 1)
	(ADC12B_CHSR) Channel 1 Status

#define	ADC12B_CHSR_CH2 (0x1u << 2)
	(ADC12B_CHSR) Channel 2 Status

#define	ADC12B_CHSR_CH3 (0x1u << 3)
	(ADC12B_CHSR) Channel 3 Status

#define	ADC12B_CHSR_CH4 (0x1u << 4)
	(ADC12B_CHSR) Channel 4 Status

#define	ADC12B_CHSR_CH5 (0x1u << 5)
	(ADC12B_CHSR) Channel 5 Status

#define	ADC12B_CHSR_CH6 (0x1u << 6)
	(ADC12B_CHSR) Channel 6 Status

#define	ADC12B_CHSR_CH7 (0x1u << 7)
	(ADC12B_CHSR) Channel 7 Status

#define	ADC12B_SR_EOC0 (0x1u << 0)
	(ADC12B_SR) End of Conversion 0

#define	ADC12B_SR_EOC1 (0x1u << 1)
	(ADC12B_SR) End of Conversion 1

#define	ADC12B_SR_EOC2 (0x1u << 2)
	(ADC12B_SR) End of Conversion 2

#define	ADC12B_SR_EOC3 (0x1u << 3)
	(ADC12B_SR) End of Conversion 3

#define	ADC12B_SR_EOC4 (0x1u << 4)
	(ADC12B_SR) End of Conversion 4

#define	ADC12B_SR_EOC5 (0x1u << 5)
	(ADC12B_SR) End of Conversion 5

#define	ADC12B_SR_EOC6 (0x1u << 6)
	(ADC12B_SR) End of Conversion 6

#define	ADC12B_SR_EOC7 (0x1u << 7)
	(ADC12B_SR) End of Conversion 7

#define	ADC12B_SR_OVRE0 (0x1u << 8)
	(ADC12B_SR) Overrun Error 0

#define	ADC12B_SR_OVRE1 (0x1u << 9)
	(ADC12B_SR) Overrun Error 1

#define	ADC12B_SR_OVRE2 (0x1u << 10)
	(ADC12B_SR) Overrun Error 2

#define	ADC12B_SR_OVRE3 (0x1u << 11)
	(ADC12B_SR) Overrun Error 3

#define	ADC12B_SR_OVRE4 (0x1u << 12)
	(ADC12B_SR) Overrun Error 4

#define	ADC12B_SR_OVRE5 (0x1u << 13)
	(ADC12B_SR) Overrun Error 5

#define	ADC12B_SR_OVRE6 (0x1u << 14)
	(ADC12B_SR) Overrun Error 6

#define	ADC12B_SR_OVRE7 (0x1u << 15)
	(ADC12B_SR) Overrun Error 7

#define	ADC12B_SR_DRDY (0x1u << 16)
	(ADC12B_SR) Data Ready

#define	ADC12B_SR_GOVRE (0x1u << 17)
	(ADC12B_SR) General Overrun Error

#define	ADC12B_SR_ENDRX (0x1u << 18)
	(ADC12B_SR) End of RX Buffer

#define	ADC12B_SR_RXBUFF (0x1u << 19)
	(ADC12B_SR) RX Buffer Full

#define	ADC12B_LCDR_LDATA_Pos 0

#define	ADC12B_LCDR_LDATA_Msk (0xfffu << ADC12B_LCDR_LDATA_Pos)
	(ADC12B_LCDR) Last Data Converted

#define	ADC12B_IER_EOC0 (0x1u << 0)
	(ADC12B_IER) End of Conversion Interrupt Enable 0

#define	ADC12B_IER_EOC1 (0x1u << 1)
	(ADC12B_IER) End of Conversion Interrupt Enable 1

#define	ADC12B_IER_EOC2 (0x1u << 2)
	(ADC12B_IER) End of Conversion Interrupt Enable 2

#define	ADC12B_IER_EOC3 (0x1u << 3)
	(ADC12B_IER) End of Conversion Interrupt Enable 3

#define	ADC12B_IER_EOC4 (0x1u << 4)
	(ADC12B_IER) End of Conversion Interrupt Enable 4

#define	ADC12B_IER_EOC5 (0x1u << 5)
	(ADC12B_IER) End of Conversion Interrupt Enable 5

#define	ADC12B_IER_EOC6 (0x1u << 6)
	(ADC12B_IER) End of Conversion Interrupt Enable 6

#define	ADC12B_IER_EOC7 (0x1u << 7)
	(ADC12B_IER) End of Conversion Interrupt Enable 7

#define	ADC12B_IER_OVRE0 (0x1u << 8)
	(ADC12B_IER) Overrun Error Interrupt Enable 0

#define	ADC12B_IER_OVRE1 (0x1u << 9)
	(ADC12B_IER) Overrun Error Interrupt Enable 1

#define	ADC12B_IER_OVRE2 (0x1u << 10)
	(ADC12B_IER) Overrun Error Interrupt Enable 2

#define	ADC12B_IER_OVRE3 (0x1u << 11)
	(ADC12B_IER) Overrun Error Interrupt Enable 3

#define	ADC12B_IER_OVRE4 (0x1u << 12)
	(ADC12B_IER) Overrun Error Interrupt Enable 4

#define	ADC12B_IER_OVRE5 (0x1u << 13)
	(ADC12B_IER) Overrun Error Interrupt Enable 5

#define	ADC12B_IER_OVRE6 (0x1u << 14)
	(ADC12B_IER) Overrun Error Interrupt Enable 6

#define	ADC12B_IER_OVRE7 (0x1u << 15)
	(ADC12B_IER) Overrun Error Interrupt Enable 7

#define	ADC12B_IER_DRDY (0x1u << 16)
	(ADC12B_IER) Data Ready Interrupt Enable

#define	ADC12B_IER_GOVRE (0x1u << 17)
	(ADC12B_IER) General Overrun Error Interrupt Enable

#define	ADC12B_IER_ENDRX (0x1u << 18)
	(ADC12B_IER) End of Receive Buffer Interrupt Enable

#define	ADC12B_IER_RXBUFF (0x1u << 19)
	(ADC12B_IER) Receive Buffer Full Interrupt Enable

#define	ADC12B_IDR_EOC0 (0x1u << 0)
	(ADC12B_IDR) End of Conversion Interrupt Disable 0

#define	ADC12B_IDR_EOC1 (0x1u << 1)
	(ADC12B_IDR) End of Conversion Interrupt Disable 1

#define	ADC12B_IDR_EOC2 (0x1u << 2)
	(ADC12B_IDR) End of Conversion Interrupt Disable 2

#define	ADC12B_IDR_EOC3 (0x1u << 3)
	(ADC12B_IDR) End of Conversion Interrupt Disable 3

#define	ADC12B_IDR_EOC4 (0x1u << 4)
	(ADC12B_IDR) End of Conversion Interrupt Disable 4

#define	ADC12B_IDR_EOC5 (0x1u << 5)
	(ADC12B_IDR) End of Conversion Interrupt Disable 5

#define	ADC12B_IDR_EOC6 (0x1u << 6)
	(ADC12B_IDR) End of Conversion Interrupt Disable 6

#define	ADC12B_IDR_EOC7 (0x1u << 7)
	(ADC12B_IDR) End of Conversion Interrupt Disable 7

#define	ADC12B_IDR_OVRE0 (0x1u << 8)
	(ADC12B_IDR) Overrun Error Interrupt Disable 0

#define	ADC12B_IDR_OVRE1 (0x1u << 9)
	(ADC12B_IDR) Overrun Error Interrupt Disable 1

#define	ADC12B_IDR_OVRE2 (0x1u << 10)
	(ADC12B_IDR) Overrun Error Interrupt Disable 2

#define	ADC12B_IDR_OVRE3 (0x1u << 11)
	(ADC12B_IDR) Overrun Error Interrupt Disable 3

#define	ADC12B_IDR_OVRE4 (0x1u << 12)
	(ADC12B_IDR) Overrun Error Interrupt Disable 4

#define	ADC12B_IDR_OVRE5 (0x1u << 13)
	(ADC12B_IDR) Overrun Error Interrupt Disable 5

#define	ADC12B_IDR_OVRE6 (0x1u << 14)
	(ADC12B_IDR) Overrun Error Interrupt Disable 6

#define	ADC12B_IDR_OVRE7 (0x1u << 15)
	(ADC12B_IDR) Overrun Error Interrupt Disable 7

#define	ADC12B_IDR_DRDY (0x1u << 16)
	(ADC12B_IDR) Data Ready Interrupt Disable

#define	ADC12B_IDR_GOVRE (0x1u << 17)
	(ADC12B_IDR) General Overrun Error Interrupt Disable

#define	ADC12B_IDR_ENDRX (0x1u << 18)
	(ADC12B_IDR) End of Receive Buffer Interrupt Disable

#define	ADC12B_IDR_RXBUFF (0x1u << 19)
	(ADC12B_IDR) Receive Buffer Full Interrupt Disable

#define	ADC12B_IMR_EOC0 (0x1u << 0)
	(ADC12B_IMR) End of Conversion Interrupt Mask 0

#define	ADC12B_IMR_EOC1 (0x1u << 1)
	(ADC12B_IMR) End of Conversion Interrupt Mask 1

#define	ADC12B_IMR_EOC2 (0x1u << 2)
	(ADC12B_IMR) End of Conversion Interrupt Mask 2

#define	ADC12B_IMR_EOC3 (0x1u << 3)
	(ADC12B_IMR) End of Conversion Interrupt Mask 3

#define	ADC12B_IMR_EOC4 (0x1u << 4)
	(ADC12B_IMR) End of Conversion Interrupt Mask 4

#define	ADC12B_IMR_EOC5 (0x1u << 5)
	(ADC12B_IMR) End of Conversion Interrupt Mask 5

#define	ADC12B_IMR_EOC6 (0x1u << 6)
	(ADC12B_IMR) End of Conversion Interrupt Mask 6

#define	ADC12B_IMR_EOC7 (0x1u << 7)
	(ADC12B_IMR) End of Conversion Interrupt Mask 7

#define	ADC12B_IMR_OVRE0 (0x1u << 8)
	(ADC12B_IMR) Overrun Error Interrupt Mask 0

#define	ADC12B_IMR_OVRE1 (0x1u << 9)
	(ADC12B_IMR) Overrun Error Interrupt Mask 1

#define	ADC12B_IMR_OVRE2 (0x1u << 10)
	(ADC12B_IMR) Overrun Error Interrupt Mask 2

#define	ADC12B_IMR_OVRE3 (0x1u << 11)
	(ADC12B_IMR) Overrun Error Interrupt Mask 3

#define	ADC12B_IMR_OVRE4 (0x1u << 12)
	(ADC12B_IMR) Overrun Error Interrupt Mask 4

#define	ADC12B_IMR_OVRE5 (0x1u << 13)
	(ADC12B_IMR) Overrun Error Interrupt Mask 5

#define	ADC12B_IMR_OVRE6 (0x1u << 14)
	(ADC12B_IMR) Overrun Error Interrupt Mask 6

#define	ADC12B_IMR_OVRE7 (0x1u << 15)
	(ADC12B_IMR) Overrun Error Interrupt Mask 7

#define	ADC12B_IMR_DRDY (0x1u << 16)
	(ADC12B_IMR) Data Ready Interrupt Mask

#define	ADC12B_IMR_GOVRE (0x1u << 17)
	(ADC12B_IMR) General Overrun Error Interrupt Mask

#define	ADC12B_IMR_ENDRX (0x1u << 18)
	(ADC12B_IMR) End of Receive Buffer Interrupt Mask

#define	ADC12B_IMR_RXBUFF (0x1u << 19)
	(ADC12B_IMR) Receive Buffer Full Interrupt Mask

#define	ADC12B_CDR_DATA_Pos 0

#define	ADC12B_CDR_DATA_Msk (0xfffu << ADC12B_CDR_DATA_Pos)
	(ADC12B_CDR[8]) Converted Data

#define	ADC12B_ACR_GAIN_Pos 0

#define	ADC12B_ACR_GAIN_Msk (0x3u << ADC12B_ACR_GAIN_Pos)
	(ADC12B_ACR) Input Gain

#define	ADC12B_ACR_GAIN(value) ((ADC12B_ACR_GAIN_Msk & ((value) << ADC12B_ACR_GAIN_Pos)))

#define	ADC12B_ACR_IBCTL_Pos 8

#define	ADC12B_ACR_IBCTL_Msk (0x3u << ADC12B_ACR_IBCTL_Pos)
	(ADC12B_ACR) Bias Current Control

#define	ADC12B_ACR_IBCTL(value) ((ADC12B_ACR_IBCTL_Msk & ((value) << ADC12B_ACR_IBCTL_Pos)))

#define	ADC12B_ACR_DIFF (0x1u << 16)
	(ADC12B_ACR) Differential Mode

#define	ADC12B_ACR_OFFSET (0x1u << 17)
	(ADC12B_ACR) Input OFFSET

#define	ADC12B_EMR_OFFMODES (0x1u << 0)
	(ADC12B_EMR) Off Mode if Sleep Bit (ADC12B_MR) = 1

#define	ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos 16

#define	ADC12B_EMR_OFF_MODE_STARTUP_TIME_Msk (0xffu << ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos)
	(ADC12B_EMR) Startup Time

#define	ADC12B_EMR_OFF_MODE_STARTUP_TIME(value) ((ADC12B_EMR_OFF_MODE_STARTUP_TIME_Msk & ((value) << ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos)))

#define	ADC12B_RPR_RXPTR_Pos 0

#define	ADC12B_RPR_RXPTR_Msk (0xffffffffu << ADC12B_RPR_RXPTR_Pos)
	(ADC12B_RPR) Receive Pointer Register

#define	ADC12B_RPR_RXPTR(value) ((ADC12B_RPR_RXPTR_Msk & ((value) << ADC12B_RPR_RXPTR_Pos)))

#define	ADC12B_RCR_RXCTR_Pos 0

#define	ADC12B_RCR_RXCTR_Msk (0xffffu << ADC12B_RCR_RXCTR_Pos)
	(ADC12B_RCR) Receive Counter Register

#define	ADC12B_RCR_RXCTR(value) ((ADC12B_RCR_RXCTR_Msk & ((value) << ADC12B_RCR_RXCTR_Pos)))

#define	ADC12B_RNPR_RXNPTR_Pos 0

#define	ADC12B_RNPR_RXNPTR_Msk (0xffffffffu << ADC12B_RNPR_RXNPTR_Pos)
	(ADC12B_RNPR) Receive Next Pointer

#define	ADC12B_RNPR_RXNPTR(value) ((ADC12B_RNPR_RXNPTR_Msk & ((value) << ADC12B_RNPR_RXNPTR_Pos)))

#define	ADC12B_RNCR_RXNCTR_Pos 0

#define	ADC12B_RNCR_RXNCTR_Msk (0xffffu << ADC12B_RNCR_RXNCTR_Pos)
	(ADC12B_RNCR) Receive Next Counter

#define	ADC12B_RNCR_RXNCTR(value) ((ADC12B_RNCR_RXNCTR_Msk & ((value) << ADC12B_RNCR_RXNCTR_Pos)))

#define	ADC12B_PTCR_RXTEN (0x1u << 0)
	(ADC12B_PTCR) Receiver Transfer Enable

#define	ADC12B_PTCR_RXTDIS (0x1u << 1)
	(ADC12B_PTCR) Receiver Transfer Disable

#define	ADC12B_PTCR_TXTEN (0x1u << 8)
	(ADC12B_PTCR) Transmitter Transfer Enable

#define	ADC12B_PTCR_TXTDIS (0x1u << 9)
	(ADC12B_PTCR) Transmitter Transfer Disable

#define	ADC12B_PTSR_RXTEN (0x1u << 0)
	(ADC12B_PTSR) Receiver Transfer Enable

#define	ADC12B_PTSR_TXTEN (0x1u << 8)
	(ADC12B_PTSR) Transmitter Transfer Enable

Detailed Description

SOFTWARE API DEFINITION FOR Analog-to-Digital-Converter 12bits

Classes

Macros

Detailed Description