Modules
	CMSIS Definitions

	Peripheral Software API

	Registers Access Definitions

	Peripheral Ids Definitions

	Peripheral Base Address Definitions

	Peripheral Pio Definitions

Macros
#define	IFLASH0_SIZE (0x20000u)

#define	IFLASH0_PAGE_SIZE (256u)

#define	IFLASH0_LOCK_REGION_SIZE (8192u)

#define	IFLASH0_NB_OF_PAGES (512u)

#define	IFLASH1_SIZE (0x20000u)

#define	IFLASH1_PAGE_SIZE (256u)

#define	IFLASH1_LOCK_REGION_SIZE (8192u)

#define	IFLASH1_NB_OF_PAGES (512u)

#define	IRAM0_SIZE (0x8000u)

#define	IRAM1_SIZE (0x4000u)

#define	NFCRAM_SIZE (0x1000u)

#define	IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE)

#define	IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE)

#define	IFLASH0_ADDR (0x00080000u)

#define	IFLASH1_ADDR (0x00100000u)

#define	IROM_ADDR (0x00180000u)

#define	IRAM0_ADDR (0x20000000u)

#define	IRAM1_ADDR (0x20080000u)

#define	NFC_RAM_ADDR (0x20100000u)

#define	UDPHS_RAM_ADDR (0x20180000u)

#define	CHIP_FREQ_SLCK_RC_MIN (20000UL)

#define	CHIP_FREQ_SLCK_RC (32000UL)

#define	CHIP_FREQ_SLCK_RC_MAX (44000UL)

#define	CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)

#define	CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)

#define	CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)

#define	CHIP_FREQ_CPU_MAX (96000000UL)

#define	CHIP_FREQ_XTAL_32K (32768UL)

#define	CHIP_FREQ_XTAL_12M (12000000UL)

#define	CHIP_FLASH_WRITE_WAIT_STATE (6U)

#define	CHIP_FREQ_FWS_0 (24000000UL)
	Maximum operating frequency when FWS is 0.

#define	CHIP_FREQ_FWS_1 (40000000UL)
	Maximum operating frequency when FWS is 1.

#define	CHIP_FREQ_FWS_2 (72000000UL)
	Maximum operating frequency when FWS is 2.

#define	CHIP_FREQ_FWS_3 (84000000UL)
	Maximum operating frequency when FWS is 3.

Typedefs
typedef volatile const uint32_t	RoReg

typedef volatile uint32_t	WoReg

typedef volatile uint32_t	RwReg

Detailed Description

This file defines all structures and symbols for SAM3U4E:

Macro Definition Documentation

#define IFLASH0_ADDR (0x00080000u)

Internal Flash 0 base address

#define IFLASH1_ADDR (0x00100000u)

Internal Flash 1 base address

#define IRAM0_ADDR (0x20000000u)

Internal RAM 0 base address

#define IRAM1_ADDR (0x20080000u)

Internal RAM 1 base address

#define IROM_ADDR (0x00180000u)

Internal ROM base address

#define NFC_RAM_ADDR (0x20100000u)

NAND Flash Controller RAM base address

#define UDPHS_RAM_ADDR (0x20180000u)

USB High Speed Device Port RAM base address

typedef volatile const uint32_t RoReg

Read only 32-bit register (volatile const unsigned int)

typedef volatile uint32_t RwReg

Read-Write 32-bit register (volatile unsigned int)

typedef volatile uint32_t WoReg

Write only 32-bit register (volatile unsigned int)