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SAM3A4C definitions

Modules

 CMSIS Definitions
 
 Peripheral Software API
 
 Registers Access Definitions
 
 Peripheral Ids Definitions
 
 Peripheral Base Address Definitions
 
 Peripheral Pio Definitions
 

Macros

#define IFLASH0_SIZE   (0x20000u)
 
#define IFLASH0_PAGE_SIZE   (256u)
 
#define IFLASH0_LOCK_REGION_SIZE   (16384u)
 
#define IFLASH0_NB_OF_PAGES   (512u)
 
#define IFLASH1_SIZE   (0x20000u)
 
#define IFLASH1_PAGE_SIZE   (256u)
 
#define IFLASH1_LOCK_REGION_SIZE   (16384u)
 
#define IFLASH1_NB_OF_PAGES   (512u)
 
#define IRAM0_SIZE   (0x8000u)
 
#define IRAM1_SIZE   (0x8000u)
 
#define IFLASH_SIZE   (IFLASH0_SIZE+IFLASH1_SIZE)
 
#define IRAM_SIZE   (IRAM0_SIZE+IRAM1_SIZE)
 
#define IFLASH0_ADDR   (0x00080000u)
 
#define IFLASH1_ADDR   (IFLASH0_ADDR+IFLASH0_SIZE)
 
#define IROM_ADDR   (0x00100000u)
 
#define IRAM0_ADDR   (0x20000000u)
 
#define IRAM1_ADDR   (0x20080000u)
 
#define NFC_RAM_ADDR   (0x20100000u)
 
#define UOTGHS_RAM_ADDR   (0x20180000u)
 
#define EBI_CS0_ADDR   (0x60000000u)
 
#define EBI_CS1_ADDR   (0x61000000u)
 
#define EBI_CS2_ADDR   (0x62000000u)
 
#define EBI_CS3_ADDR   (0x63000000u)
 
#define EBI_CS4_ADDR   (0x64000000u)
 
#define EBI_CS5_ADDR   (0x65000000u)
 
#define EBI_CS6_ADDR   (0x66000000u)
 
#define EBI_CS7_ADDR   (0x67000000u)
 
#define CHIP_FREQ_SLCK_RC_MIN   (20000UL)
 
#define CHIP_FREQ_SLCK_RC   (32000UL)
 
#define CHIP_FREQ_SLCK_RC_MAX   (44000UL)
 
#define CHIP_FREQ_MAINCK_RC_4MHZ   (4000000UL)
 
#define CHIP_FREQ_MAINCK_RC_8MHZ   (8000000UL)
 
#define CHIP_FREQ_MAINCK_RC_12MHZ   (12000000UL)
 
#define CHIP_FREQ_CPU_MAX   (84000000UL)
 
#define CHIP_FREQ_XTAL_32K   (32768UL)
 
#define CHIP_FREQ_XTAL_12M   (12000000UL)
 
#define CHIP_FLASH_WRITE_WAIT_STATE   (6U)
 
#define CHIP_FREQ_FWS_0   (22500000UL)
 Maximum operating frequency when FWS is 0.
 
#define CHIP_FREQ_FWS_1   (34000000UL)
 Maximum operating frequency when FWS is 1.
 
#define CHIP_FREQ_FWS_2   (53000000UL)
 Maximum operating frequency when FWS is 2.
 
#define CHIP_FREQ_FWS_3   (78000000UL)
 Maximum operating frequency when FWS is 3.
 

Typedefs

typedef volatile const uint32_t RoReg
 
typedef volatile uint32_t WoReg
 
typedef volatile uint32_t RwReg
 

Detailed Description

This file defines all structures and symbols for SAM3A4C:

Macro Definition Documentation

#define EBI_CS0_ADDR   (0x60000000u)

EBI Chip Select 0 base address

#define EBI_CS1_ADDR   (0x61000000u)

EBI Chip Select 1 base address

#define EBI_CS2_ADDR   (0x62000000u)

EBI Chip Select 2 base address

#define EBI_CS3_ADDR   (0x63000000u)

EBI Chip Select 3 base address

#define EBI_CS4_ADDR   (0x64000000u)

EBI Chip Select 4 base address

#define EBI_CS5_ADDR   (0x65000000u)

EBI Chip Select 5 base address

#define EBI_CS6_ADDR   (0x66000000u)

EBI Chip Select 6 base address

#define EBI_CS7_ADDR   (0x67000000u)

EBI Chip Select 7 base address

#define IFLASH0_ADDR   (0x00080000u)

Internal Flash 0 base address

#define IFLASH1_ADDR   (IFLASH0_ADDR+IFLASH0_SIZE)

Internal Flash 1 base address

#define IRAM0_ADDR   (0x20000000u)

Internal RAM 0 base address

#define IRAM1_ADDR   (0x20080000u)

Internal RAM 1 base address

#define IROM_ADDR   (0x00100000u)

Internal ROM base address

#define NFC_RAM_ADDR   (0x20100000u)

NAND Flash Controller RAM base address

#define UOTGHS_RAM_ADDR   (0x20180000u)

USB On-The-Go Interface RAM base address

Typedef Documentation

typedef volatile const uint32_t RoReg

Read only 32-bit register (volatile const unsigned int)

typedef volatile uint32_t RwReg

Read-Write 32-bit register (volatile unsigned int)

typedef volatile uint32_t WoReg

Write only 32-bit register (volatile unsigned int)